Lines Matching +full:cam0 +full:- +full:default +full:- +full:state
17 * - MCMDR.FDUP (full duplex) is ignored, half duplex is not supported
18 * - Only CAM0 is supported, CAM[1-15] are not
19 * - writes to CAMEN.[1-15] are ignored, these bits always read as zeroes
20 * - MII is not implemented, MIIDA.BUSY and MIID always return zero
21 * - MCMDR.LBK is not implemented
22 * - MCMDR.{OPMOD,ENSQE,AEP,ARP} are not supported
23 * - H/W FIFOs are not supported, MCMDR.FFTCR is ignored
24 * - MGSTA.SQE is not supported
25 * - pause and control frames are not implemented
26 * - MGSTA.CCNT is not supported
27 * - MPCNT, DMARFS are not implemented
35 #include "hw/qdev-clock.h"
36 #include "hw/qdev-properties.h"
41 #include "qemu/error-report.h"
87 /* Only CAM0 is supported, fold the others into something simple. */ in emc_reg_name()
93 default: return "UNKNOWN"; in emc_reg_name()
102 trace_npcm7xx_emc_reset(emc->emc_num); in emc_reset()
104 memset(&emc->regs[0], 0, sizeof(emc->regs)); in emc_reset()
106 /* These regs have non-zero reset values. */ in emc_reset()
107 emc->regs[REG_TXDLSA] = 0xfffffffc; in emc_reset()
108 emc->regs[REG_RXDLSA] = 0xfffffffc; in emc_reset()
109 emc->regs[REG_MIIDA] = 0x00900000; in emc_reset()
110 emc->regs[REG_FFTCR] = 0x0101; in emc_reset()
111 emc->regs[REG_DMARFC] = 0x0800; in emc_reset()
112 emc->regs[REG_MPCNT] = 0x7fff; in emc_reset()
114 emc->tx_active = false; in emc_reset()
115 emc->rx_active = false; in emc_reset()
118 value = (emc->conf.macaddr.a[0] << 24) | in emc_reset()
119 (emc->conf.macaddr.a[1] << 16) | in emc_reset()
120 (emc->conf.macaddr.a[2] << 8) | in emc_reset()
121 emc->conf.macaddr.a[3]; in emc_reset()
122 emc->regs[REG_CAMM_BASE] = value; in emc_reset()
124 value = (emc->conf.macaddr.a[4] << 24) | (emc->conf.macaddr.a[5] << 16); in emc_reset()
125 emc->regs[REG_CAML_BASE] = value; in emc_reset()
140 uint32_t mcmdr = emc->regs[REG_MCMDR]; in emc_soft_reset()
142 emc->regs[REG_MCMDR] = mcmdr & (REG_MCMDR_LBK | REG_MCMDR_OPMOD); in emc_soft_reset()
144 qemu_set_irq(emc->tx_irq, 0); in emc_soft_reset()
145 qemu_set_irq(emc->rx_irq, 0); in emc_soft_reset()
160 if (emc->regs[REG_MISTA] & emc->regs[REG_MIEN] & mask) { in emc_update_mista_txintr()
161 emc->regs[REG_MISTA] |= REG_MISTA_TXINTR; in emc_update_mista_txintr()
163 emc->regs[REG_MISTA] &= ~REG_MISTA_TXINTR; in emc_update_mista_txintr()
174 if (emc->regs[REG_MISTA] & emc->regs[REG_MIEN] & mask) { in emc_update_mista_rxintr()
175 emc->regs[REG_MISTA] |= REG_MISTA_RXINTR; in emc_update_mista_rxintr()
177 emc->regs[REG_MISTA] &= ~REG_MISTA_RXINTR; in emc_update_mista_rxintr()
184 int level = !!(emc->regs[REG_MISTA] & in emc_update_tx_irq()
185 emc->regs[REG_MIEN] & in emc_update_tx_irq()
188 qemu_set_irq(emc->tx_irq, level); in emc_update_tx_irq()
194 int level = !!(emc->regs[REG_MISTA] & in emc_update_rx_irq()
195 emc->regs[REG_MIEN] & in emc_update_rx_irq()
198 qemu_set_irq(emc->rx_irq, level); in emc_update_rx_irq()
217 return -1; in emc_read_tx_desc()
219 desc->flags = le32_to_cpu(desc->flags); in emc_read_tx_desc()
220 desc->txbsa = le32_to_cpu(desc->txbsa); in emc_read_tx_desc()
221 desc->status_and_length = le32_to_cpu(desc->status_and_length); in emc_read_tx_desc()
222 desc->ntxdsa = le32_to_cpu(desc->ntxdsa); in emc_read_tx_desc()
230 le_desc.flags = cpu_to_le32(desc->flags); in emc_write_tx_desc()
231 le_desc.txbsa = cpu_to_le32(desc->txbsa); in emc_write_tx_desc()
232 le_desc.status_and_length = cpu_to_le32(desc->status_and_length); in emc_write_tx_desc()
233 le_desc.ntxdsa = cpu_to_le32(desc->ntxdsa); in emc_write_tx_desc()
238 return -1; in emc_write_tx_desc()
249 return -1; in emc_read_rx_desc()
251 desc->status_and_length = le32_to_cpu(desc->status_and_length); in emc_read_rx_desc()
252 desc->rxbsa = le32_to_cpu(desc->rxbsa); in emc_read_rx_desc()
253 desc->reserved = le32_to_cpu(desc->reserved); in emc_read_rx_desc()
254 desc->nrxdsa = le32_to_cpu(desc->nrxdsa); in emc_read_rx_desc()
262 le_desc.status_and_length = cpu_to_le32(desc->status_and_length); in emc_write_rx_desc()
263 le_desc.rxbsa = cpu_to_le32(desc->rxbsa); in emc_write_rx_desc()
264 le_desc.reserved = cpu_to_le32(desc->reserved); in emc_write_rx_desc()
265 le_desc.nrxdsa = cpu_to_le32(desc->nrxdsa); in emc_write_rx_desc()
270 return -1; in emc_write_rx_desc()
278 emc->regs[REG_MISTA] |= flags; in emc_set_mista()
289 emc->tx_active = false; in emc_halt_tx()
295 emc->rx_active = false; in emc_halt_rx()
301 emc->rx_active = true; in emc_enable_rx_and_flush()
302 qemu_flush_queued_packets(qemu_get_queue(emc->nic)); in emc_enable_rx_and_flush()
317 emc->regs[REG_CTXDSA] = TX_DESC_NTXDSA(tx_desc->ntxdsa); in emc_set_next_tx_descriptor()
332 emc->regs[REG_CRXDSA] = RX_DESC_NRXDSA(rx_desc->nrxdsa); in emc_set_next_rx_descriptor()
340 uint32_t desc_addr = TX_DESC_NTXDSA(emc->regs[REG_CTXDSA]); in emc_try_send_next_packet()
372 emc->regs[REG_CTXBSA] = next_buf_addr; in emc_try_send_next_packet()
388 trace_npcm7xx_emc_tx_done(emc->regs[REG_CTXDSA]); in emc_try_send_next_packet()
393 memset(buf + length, 0, MIN_PACKET_LENGTH - length); in emc_try_send_next_packet()
398 qemu_send_packet(qemu_get_queue(emc->nic), buf, length); in emc_try_send_next_packet()
405 if (emc->regs[REG_MISTA] & emc->regs[REG_MIEN] & REG_MISTA_TXINTR) { in emc_try_send_next_packet()
411 trace_npcm7xx_emc_tx_done(emc->regs[REG_CTXDSA]); in emc_try_send_next_packet()
418 bool can_receive = emc->rx_active; in emc_can_receive()
431 if (emc->regs[REG_CAMCMR] & REG_CAMCMR_CCAM) { in emc_receive_filter1()
435 return !!(emc->regs[REG_CAMCMR] & REG_CAMCMR_ABP); in emc_receive_filter1()
438 if (emc->regs[REG_CAMCMR] & REG_CAMCMR_CCAM) { in emc_receive_filter1()
442 return !!(emc->regs[REG_CAMCMR] & REG_CAMCMR_AMP); in emc_receive_filter1()
448 if (emc->regs[REG_CAMCMR] & REG_CAMCMR_AUP) { in emc_receive_filter1()
452 value = emc->regs[REG_CAMM_BASE]; in emc_receive_filter1()
457 value = emc->regs[REG_CAML_BASE]; in emc_receive_filter1()
461 matches = ((emc->regs[REG_CAMCMR] & REG_CAMCMR_ECMP) && in emc_receive_filter1()
462 /* We only support one CAM register, CAM0. */ in emc_receive_filter1()
463 (emc->regs[REG_CAMEN] & (1 << 0)) && in emc_receive_filter1()
465 if (emc->regs[REG_CAMCMR] & REG_CAMCMR_CCAM) { in emc_receive_filter1()
473 default: in emc_receive_filter1()
505 return -1; in emc_receive()
510 len > 0xffff - CRC_LENGTH) { in emc_receive()
528 max_frame_len = REG_DMARFC_RXMS(emc->regs[REG_DMARFC]); in emc_receive()
542 if (emc->regs[REG_MCMDR] & REG_MCMDR_ALP) { in emc_receive()
552 desc_addr = RX_DESC_NRXDSA(emc->regs[REG_CRXDSA]); in emc_receive()
570 if (!(emc->regs[REG_MCMDR] & REG_MCMDR_SPCRC)) { in emc_receive()
578 emc->regs[REG_CRXBSA] = buf_addr; in emc_receive()
581 (!(emc->regs[REG_MCMDR] & REG_MCMDR_SPCRC) && in emc_receive()
589 trace_npcm7xx_emc_rx_done(emc->regs[REG_CRXDSA]); in emc_receive()
597 if (!(emc->regs[REG_MCMDR] & REG_MCMDR_SPCRC)) { in emc_receive()
603 if (emc->regs[REG_MISTA] & emc->regs[REG_MIEN] & REG_MISTA_RXINTR) { in emc_receive()
612 trace_npcm7xx_emc_rx_done(emc->regs[REG_CRXDSA]); in emc_receive()
641 "%s: Read of write-only reg, %s/%d\n", in npcm7xx_emc_read()
644 default: in npcm7xx_emc_read()
645 result = emc->regs[reg]; in npcm7xx_emc_read()
649 trace_npcm7xx_emc_reg_read(emc->emc_num, result, emc_reg_name(reg), reg); in npcm7xx_emc_read()
669 trace_npcm7xx_emc_reg_write(emc->emc_num, emc_reg_name(reg), reg, value); in npcm7xx_emc_write()
673 emc->regs[reg] = value; in npcm7xx_emc_write()
676 /* Only CAM0 is supported, don't pretend otherwise. */ in npcm7xx_emc_write()
679 "%s: Only CAM0 is supported, cannot enable others" in npcm7xx_emc_write()
683 emc->regs[reg] = value & 1; in npcm7xx_emc_write()
686 emc->regs[reg] = value; in npcm7xx_emc_write()
689 emc->regs[reg] = value; in npcm7xx_emc_write()
698 prev = emc->regs[reg]; in npcm7xx_emc_write()
699 emc->regs[reg] = value; in npcm7xx_emc_write()
700 /* Update tx state. */ in npcm7xx_emc_write()
703 emc->regs[REG_CTXDSA] = emc->regs[REG_TXDLSA]; in npcm7xx_emc_write()
711 emc->regs[REG_MGSTA] |= REG_MGSTA_TXHA; in npcm7xx_emc_write()
716 /* Update rx state. */ in npcm7xx_emc_write()
719 emc->regs[REG_CRXDSA] = emc->regs[REG_RXDLSA]; in npcm7xx_emc_write()
722 emc->regs[REG_MGSTA] |= REG_MGSTA_RXHA; in npcm7xx_emc_write()
735 emc->regs[reg] = value; in npcm7xx_emc_write()
738 emc->regs[reg] = value; in npcm7xx_emc_write()
743 emc->regs[reg] &= ~value; in npcm7xx_emc_write()
748 emc->regs[reg] &= ~value; in npcm7xx_emc_write()
751 if (emc->regs[REG_MCMDR] & REG_MCMDR_TXON) { in npcm7xx_emc_write()
752 emc->tx_active = true; in npcm7xx_emc_write()
754 while (emc->tx_active) { in npcm7xx_emc_write()
760 if (emc->regs[REG_MCMDR] & REG_MCMDR_RXON) { in npcm7xx_emc_write()
765 emc->regs[reg] = value & ~REG_MIIDA_BUSY; in npcm7xx_emc_write()
775 "%s: Write to read-only reg %s/%d\n", in npcm7xx_emc_write()
778 default: in npcm7xx_emc_write()
815 memory_region_init_io(&emc->iomem, OBJECT(emc), &npcm7xx_emc_ops, emc, in npcm7xx_emc_realize()
817 sysbus_init_mmio(sbd, &emc->iomem); in npcm7xx_emc_realize()
818 sysbus_init_irq(sbd, &emc->tx_irq); in npcm7xx_emc_realize()
819 sysbus_init_irq(sbd, &emc->rx_irq); in npcm7xx_emc_realize()
821 qemu_macaddr_default_if_unset(&emc->conf.macaddr); in npcm7xx_emc_realize()
822 emc->nic = qemu_new_nic(&net_npcm7xx_emc_info, &emc->conf, in npcm7xx_emc_realize()
823 object_get_typename(OBJECT(dev)), dev->id, in npcm7xx_emc_realize()
824 &dev->mem_reentrancy_guard, emc); in npcm7xx_emc_realize()
825 qemu_format_nic_info_str(qemu_get_queue(emc->nic), emc->conf.macaddr.a); in npcm7xx_emc_realize()
832 qemu_del_nic(emc->nic); in npcm7xx_emc_unrealize()
857 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); in npcm7xx_emc_class_init()
858 dc->desc = "NPCM7xx EMC Controller"; in npcm7xx_emc_class_init()
859 dc->realize = npcm7xx_emc_realize; in npcm7xx_emc_class_init()
860 dc->unrealize = npcm7xx_emc_unrealize; in npcm7xx_emc_class_init()
862 dc->vmsd = &vmstate_npcm7xx_emc; in npcm7xx_emc_class_init()