Lines Matching +full:merge +full:- +full:fifo +full:- +full:en
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
27 * https://www.microsemi.com/document-portal/cat_view/56661-internal-documents/
28 * 56758-soc?lang=en&limit=20&limitstart=220
35 #include "hw/net/msf2-emac.h"
38 #include "hw/qdev-properties.h"
67 FIELD(DMA_TX_CTL, EN, 0, 1)
74 FIELD(DMA_RX_CTL, EN, 0, 1)
96 uint32_t ier = s->regs[R_DMA_IRQ_MASK]; in emac_get_isr()
97 uint32_t tx = s->regs[R_DMA_TX_STATUS] & 0xF; in emac_get_isr()
98 uint32_t rx = s->regs[R_DMA_RX_STATUS] & 0xF; in emac_get_isr()
101 s->regs[R_DMA_IRQ] = ier & isr; in emac_get_isr()
102 return s->regs[R_DMA_IRQ]; in emac_get_isr()
109 qemu_set_irq(s->irq, intr); in emac_update_irq()
114 address_space_read(&s->dma_as, desc, MEMTXATTRS_UNSPECIFIED, d, sizeof *d); in emac_load_desc()
116 d->pktaddr = le32_to_cpu(d->pktaddr); in emac_load_desc()
117 d->pktsize = le32_to_cpu(d->pktsize); in emac_load_desc()
118 d->next = le32_to_cpu(d->next); in emac_load_desc()
128 outd.pktaddr = cpu_to_le32(d->pktaddr); in emac_store_desc()
129 outd.pktsize = cpu_to_le32(d->pktsize); in emac_store_desc()
130 outd.next = cpu_to_le32(d->next); in emac_store_desc()
132 address_space_write(&s->dma_as, desc, MEMTXATTRS_UNSPECIFIED, &outd, sizeof outd); in emac_store_desc()
137 NetClientState *nc = qemu_get_queue(s->nic); in msf2_dma_tx()
138 hwaddr desc = s->regs[R_DMA_TX_DESC]; in msf2_dma_tx()
145 if (!(s->regs[R_CFG1] & R_CFG1_TX_EN_MASK)) { in msf2_dma_tx()
155 address_space_read(&s->dma_as, d.pktaddr, MEMTXATTRS_UNSPECIFIED, in msf2_dma_tx()
159 * a FIFO and packets should be sent out from FIFO only when in msf2_dma_tx()
162 if (s->regs[R_CFG1] & R_CFG1_LB_EN_MASK) { in msf2_dma_tx()
170 status = s->regs[R_DMA_TX_STATUS]; in msf2_dma_tx()
173 s->regs[R_DMA_TX_STATUS] = FIELD_DP32(status, DMA_TX_STATUS, in msf2_dma_tx()
175 s->regs[R_DMA_TX_STATUS] |= R_DMA_TX_STATUS_PKT_SENT_MASK; in msf2_dma_tx()
178 s->regs[R_DMA_TX_STATUS] |= R_DMA_TX_STATUS_UNDERRUN_MASK; in msf2_dma_tx()
179 s->regs[R_DMA_TX_CTL] &= ~R_DMA_TX_CTL_EN_MASK; in msf2_dma_tx()
185 if (qemu_get_queue(s->nic)->link_down) { in msf2_phy_update_link()
186 s->phy_regs[MII_BMSR] &= ~(MII_BMSR_AN_COMP | in msf2_phy_update_link()
189 s->phy_regs[MII_BMSR] |= (MII_BMSR_AN_COMP | in msf2_phy_update_link()
196 memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); in msf2_phy_reset()
197 s->phy_regs[MII_BMCR] = 0x1140; in msf2_phy_reset()
198 s->phy_regs[MII_BMSR] = 0x7968; in msf2_phy_reset()
199 s->phy_regs[MII_PHYID1] = 0x0022; in msf2_phy_reset()
200 s->phy_regs[MII_PHYID2] = 0x1550; in msf2_phy_reset()
201 s->phy_regs[MII_ANAR] = 0x01E1; in msf2_phy_reset()
202 s->phy_regs[MII_ANLPAR] = 0xCDE1; in msf2_phy_reset()
209 uint8_t reg_addr = s->regs[R_MII_ADDR] & R_MII_ADDR_REGADDR_MASK; in write_to_phy()
210 uint8_t phy_addr = (s->regs[R_MII_ADDR] >> R_MII_ADDR_PHYADDR_SHIFT) & in write_to_phy()
212 uint16_t data = s->regs[R_MII_CTL] & 0xFFFF; in write_to_phy()
228 s->phy_regs[MII_BMSR] |= MII_BMSR_AN_COMP; in write_to_phy()
233 s->phy_regs[reg_addr] = data; in write_to_phy()
238 uint8_t reg_addr = s->regs[R_MII_ADDR] & R_MII_ADDR_REGADDR_MASK; in read_from_phy()
239 uint8_t phy_addr = (s->regs[R_MII_ADDR] >> R_MII_ADDR_PHYADDR_SHIFT) & in read_from_phy()
243 return s->phy_regs[reg_addr]; in read_from_phy()
251 memset(&s->regs[0], 0, sizeof(s->regs)); in msf2_emac_do_reset()
252 s->regs[R_CFG1] = 0x80000000; in msf2_emac_do_reset()
253 s->regs[R_CFG2] = 0x00007000; in msf2_emac_do_reset()
254 s->regs[R_IFG] = 0x40605060; in msf2_emac_do_reset()
255 s->regs[R_HALF_DUPLEX] = 0x00A1F037; in msf2_emac_do_reset()
256 s->regs[R_MAX_FRAME_LENGTH] = 0x00000600; in msf2_emac_do_reset()
257 s->regs[R_FIFO_CFG5] = 0X3FFFF; in msf2_emac_do_reset()
274 if (addr >= ARRAY_SIZE(s->regs)) { in emac_read()
280 r = s->regs[addr]; in emac_read()
297 s->regs[addr] = value; in emac_write()
303 s->regs[addr] = value; in emac_write()
305 s->rx_desc = s->regs[R_DMA_RX_DESC]; in emac_write()
306 qemu_flush_queued_packets(qemu_get_queue(s->nic)); in emac_write()
310 s->regs[addr] = value; in emac_write()
319 * *ENRPLY bits immediately. Also the reset bits to reset PE-MCXMAC in emac_write()
321 * inter-packet gap and control frames. in emac_write()
324 s->regs[addr] = deposit32(value, 16, 5, enreqbits); in emac_write()
332 s->regs[addr] = value & ~3; in emac_write()
340 s->regs[addr] = value & ~3; in emac_write()
344 s->regs[addr] &= ~R_DMA_TX_STATUS_UNDERRUN_MASK; in emac_write()
347 pktcnt = FIELD_EX32(s->regs[addr], DMA_TX_STATUS, PKTCNT); in emac_write()
348 pktcnt--; in emac_write()
349 s->regs[addr] = FIELD_DP32(s->regs[addr], DMA_TX_STATUS, in emac_write()
352 s->regs[addr] &= ~R_DMA_TX_STATUS_PKT_SENT_MASK; in emac_write()
358 s->regs[addr] &= ~R_DMA_RX_STATUS_OVERFLOW_MASK; in emac_write()
361 pktcnt = FIELD_EX32(s->regs[addr], DMA_RX_STATUS, PKTCNT); in emac_write()
362 pktcnt--; in emac_write()
363 s->regs[addr] = FIELD_DP32(s->regs[addr], DMA_RX_STATUS, in emac_write()
366 s->regs[addr] &= ~R_DMA_RX_STATUS_PKT_RCVD_MASK; in emac_write()
374 s->regs[R_MII_STS] = read_from_phy(s); in emac_write()
378 s->regs[addr] = value; in emac_write()
382 s->regs[addr] = value; in emac_write()
389 stl_be_p(s->mac_addr, value); in emac_write()
392 s->regs[addr] = value; in emac_write()
397 stw_be_p(s->mac_addr + 4, value >> 16); in emac_write()
400 if (addr >= ARRAY_SIZE(s->regs)) { in emac_write()
406 s->regs[addr] = value; in emac_write()
426 return (s->regs[R_CFG1] & R_CFG1_RX_EN_MASK) && in emac_can_rx()
427 (s->regs[R_DMA_RX_CTL] & R_DMA_RX_CTL_EN_MASK); in emac_can_rx()
438 if (s->regs[R_FIFO_CFG5] & R_FIFO_CFG5_BCAST_MASK) { in addr_filter_ok()
440 } else if (s->regs[R_FIFO_CFG4] & R_FIFO_CFG4_BCAST_MASK) { in addr_filter_ok()
444 if (s->regs[R_FIFO_CFG5] & R_FIFO_CFG5_MCAST_MASK) { in addr_filter_ok()
446 } else if (s->regs[R_FIFO_CFG4] & R_FIFO_CFG4_MCAST_MASK) { in addr_filter_ok()
458 return !memcmp(buf, s->mac_addr, sizeof(s->mac_addr)); in addr_filter_ok()
468 if (size > (s->regs[R_MAX_FRAME_LENGTH] & 0xFFFF)) { in emac_rx()
475 emac_load_desc(s, &d, s->rx_desc); in emac_rx()
478 address_space_write(&s->dma_as, d.pktaddr, MEMTXATTRS_UNSPECIFIED, in emac_rx()
481 emac_store_desc(s, &d, s->rx_desc); in emac_rx()
483 status = s->regs[R_DMA_RX_STATUS]; in emac_rx()
486 s->regs[R_DMA_RX_STATUS] = FIELD_DP32(status, DMA_RX_STATUS, in emac_rx()
488 s->regs[R_DMA_RX_STATUS] |= R_DMA_RX_STATUS_PKT_RCVD_MASK; in emac_rx()
489 s->rx_desc = d.next; in emac_rx()
491 s->regs[R_DMA_RX_CTL] &= ~R_DMA_RX_CTL_EN_MASK; in emac_rx()
492 s->regs[R_DMA_RX_STATUS] |= R_DMA_RX_STATUS_OVERFLOW_MASK; in emac_rx()
524 if (!s->dma_mr) { in msf2_emac_realize()
525 error_setg(errp, "MSS_EMAC 'ahb-bus' link not set"); in msf2_emac_realize()
529 address_space_init(&s->dma_as, s->dma_mr, "emac-ahb"); in msf2_emac_realize()
531 qemu_macaddr_default_if_unset(&s->conf.macaddr); in msf2_emac_realize()
532 s->nic = qemu_new_nic(&net_msf2_emac_info, &s->conf, in msf2_emac_realize()
533 object_get_typename(OBJECT(dev)), dev->id, in msf2_emac_realize()
534 &dev->mem_reentrancy_guard, s); in msf2_emac_realize()
535 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); in msf2_emac_realize()
542 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); in msf2_emac_init()
544 memory_region_init_io(&s->mmio, obj, &emac_ops, s, in msf2_emac_init()
545 "msf2-emac", R_MAX * 4); in msf2_emac_init()
546 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); in msf2_emac_init()
550 DEFINE_PROP_LINK("ahb-bus", MSF2EmacState, dma_mr,
573 dc->realize = msf2_emac_realize; in msf2_emac_class_init()
575 dc->vmsd = &vmstate_msf2_emac; in msf2_emac_class_init()