hw/net/igb_regs.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
51 /* Receive Descriptor - Advanced */
94 /* Enable flexible speed on link-up */
107 #define IGP02E1000_AGC_LENGTH_SHIFT       9   /* Course - 15:13, Fine - 12:9 */
121 /* TX/RX descriptor defines */
186 #define E1000_TXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Tx Queue */
201 #define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
202 #define E1000_DCA_TXCTRL_DESC_DCA_EN BIT(5) /* DCA Tx Desc enable */
203 #define E1000_DCA_TXCTRL_DESC_RRO_EN BIT(9) /* Tx rd Desc Relax Order */
204 #define E1000_DCA_TXCTRL_TX_WB_RO_EN BIT(11) /* Tx Desc writeback RO bit */
205 #define E1000_DCA_TXCTRL_DATA_RRO_EN BIT(13) /* Tx rd data Relax Order */
208 #define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
210 #define E1000_DCA_TXCTRL_CPUID_SHIFT 24 /* Tx CPUID now in the last byte */
287 #define E1000_TCTL_EN     0x00000002    /* enable tx */
291 #define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
315 #define E1000_EICR_TX_QUEUE0    0x00000100 /* Tx Queue 0 Interrupt */
316 #define E1000_EICR_TX_QUEUE1    0x00000200 /* Tx Queue 1 Interrupt */
317 #define E1000_EICR_TX_QUEUE2    0x00000400 /* Tx Queue 2 Interrupt */
318 #define E1000_EICR_TX_QUEUE3    0x00000800 /* Tx Queue 3 Interrupt */
325 #define E1000_TSYNCTXCTL_VALID    0x00000001 /* tx timestamp valid */
326 #define E1000_TSYNCTXCTL_ENABLED  0x00000010 /* enable tx timestampping */
335 #define MAX_PHY_REG_ADDRESS    0x1F  /* 5 bit address bus (0-0x1F) */
344 #define E1000_P2VMAILBOX_VFU  0x00000004 /* VF owns the mailbox buffer */
345 #define E1000_P2VMAILBOX_PFU  0x00000008 /* PF owns the mailbox buffer */
346 #define E1000_P2VMAILBOX_RVFU 0x00000010 /* Reset VFU - used when VF stuck */
353 #define E1000_V2PMAILBOX_SIZE 16 /* 16 32 bit words - 64 bytes */
386 #define E1000_EICR      0x01580  /* Ext. Interrupt Cause Read - R/clr */
388 #define E1000_EICS      0x01520  /* Ext. Interrupt Cause Set - W0 */
389 #define E1000_EIMS      0x01524  /* Ext. Interrupt Mask Set/Read - RW */
390 #define E1000_EIMC      0x01528  /* Ext. Interrupt Mask Clear - WO */
391 #define E1000_EIAC      0x0152C  /* Ext. Interrupt Auto Clear - RW */
392 #define E1000_EIAM      0x01530  /* Ext. Interrupt Ack Auto Clear Mask - RW */
394 #define E1000_IVAR0     0x01700  /* Interrupt Vector Allocation Register - RW */
395 #define E1000_IVAR_MISC 0x01740  /* Interrupt Vector Allocation Register (last) - RW */
396 #define E1000_FRTIMER   0x01048  /* Free Running Timer - RW */
397 #define E1000_FCRTV     0x02460  /* Flow Control Refresh Timer Value - RW */
399 #define E1000_TSYNCRXCFG 0x05F50 /* Time Sync Rx Configuration - RW */
415 #define E1000_RXPBS 0x02404  /* Rx Packet Buffer Size - RW */
416 #define E1000_TXPBS 0x03404  /* Tx Packet Buffer Size - RW */
418 #define E1000_DTXCTL 0x03590  /* DMA TX Control - RW */
420 #define E1000_HTCBDPC     0x04124  /* Host TX Circuit Breaker Dropped Count */
422 #define E1000_RA2         0x054E0  /* 2nd half of Rx address array - RW Array */
424 #define E1000_VT_CTL   0x0581C  /* VMDq Control - RW */
427 #define E1000_MBVFICR   0x00C80 /* Mailbox VF Cause - RWC */
428 #define E1000_MBVFIMR   0x00C84 /* Mailbox VF int Mask - RW */
429 #define E1000_VFLRE     0x00C88 /* VF Register Events - RWC */
432 #define E1000_QDE       0x02408 /* Queue Drop Enable - RW */
433 #define E1000_DTXSWC    0x03500 /* DMA Tx Switch Control - RW */
434 #define E1000_WVBR      0x03554 /* VM Wrong Behavior - RWS */
435 #define E1000_RPLOLR    0x05AF0 /* Replication Offload - RW */
436 #define E1000_UTA       0x0A000 /* Unicast Table Array - RW */
438 #define E1000_TXSWC     0x05ACC /* Tx Switch Control */
467 #define E1000_V2PMAILBOX_VFU      0x00000004 /* VF owns the mailbox buffer */
468 #define E1000_V2PMAILBOX_PFU      0x00000008 /* PF owns the mailbox buffer */
475 #define E1000_VFMAILBOX_SIZE      16 /* 16 32 bit words - 64 bytes */
489 /* We have a total wait time of 1s for vf mailbox posted messages */
490 #define E1000_VF_MBX_INIT_TIMEOUT 2000 /* retry count for mbx timeout */
566 /* RX Queue Drop Packet Count; RC */
571 /* TX Descriptor Base Low; RW */
575 /* TX Descriptor Base High; RW */
579 /* TX Descriptor Ring Length; RW */
583 /* TX Descriptor Head; RW */
587 /* TX DCA Control; RW */
591 /* TX Descriptor Tail; RW */
595 /* TX Descriptor Control; RW */
599 /* TX Descriptor Completion Write–Back Address Low; RW */
603 /* TX Descriptor Completion Write–Back Address High; RW */
609 #define E1000_XDBAL_MASK (~(BIT(5) - 1)) /* TDBAL and RDBAL Registers Mask */
628 #define E1000_EICR_MSIX_MASK   0x01FFFFFF /* Bits used in MSI-X mode */
629 #define E1000_EICR_LEGACY_MASK 0x4000FFFF /* Bits used in non MSI-X mode */
634 /* Mirror Good Packets Received Count; RO */
637 /* Mirror Good Packets Transmitted Count; RO */
640 /* Mirror Good Octets Received Count; RO */
658 /* Mirror Good Octets Transmitted Count; RO */
661 /* Mirror Multicast Packets Received Count; RO */
664 /* Mirror Good RX Packets loopback Count; RO */
667 /* Mirror Good TX packets loopback Count; RO */
670 /* Mirror Good RX Octets loopback Count; RO */
673 /* Mirror Good TX Octets loopback Count; RO */
705 #define E1000_ADVRXD_HDR_LEN_OFFSET    (21 - 16)
706 #define E1000_ADVRXD_ADV_HDR_LEN_MASK  ((BIT(10) - 1) << \
713     return i < 8 ? i * 4 : (i - 8) * 4 + 2;  in igb_ivar_entry_rx()
718     return i < 8 ? i * 4 + 1 : (i - 8) * 4 + 3;  in igb_ivar_entry_tx()