Lines Matching refs:mac
104 e1000x_inc_reg_if_not_full(core->mac, IAC); in igb_raise_legacy_irq()
137 trace_e1000e_irq_icr_clear_eiac(core->mac[EICR], core->mac[EIAC]); in igb_msix_notify()
138 effective_eiac = core->mac[EIAC] & BIT(cause); in igb_msix_notify()
139 core->mac[EICR] &= ~effective_eiac; in igb_msix_notify()
145 int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] * in igb_intrmgr_rearm_timer()
239 return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true; in igb_rx_csum_enabled()
264 return core->mac[E1000_SRRCTL(r->idx) >> 2] & E1000_SRRCTL_DESCTYPE_MASK; in igb_rx_queue_desctyp_get()
278 return (core->mac[MRQC] & 3) == E1000_MRQC_ENABLE_RSS_MQ && in igb_rss_enabled()
301 trace_e1000e_rx_rss_ip4(l4hdr_proto, core->mac[MRQC], in igb_rss_get_hash_type()
302 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]), in igb_rss_get_hash_type()
303 E1000_MRQC_EN_IPV4(core->mac[MRQC])); in igb_rss_get_hash_type()
306 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) { in igb_rss_get_hash_type()
311 (core->mac[MRQC] & E1000_MRQC_RSS_FIELD_IPV4_UDP)) { in igb_rss_get_hash_type()
315 if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) { in igb_rss_get_hash_type()
321 bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS; in igb_rss_get_hash_type()
322 bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS; in igb_rss_get_hash_type()
331 trace_e1000e_rx_rss_ip6_rfctl(core->mac[RFCTL]); in igb_rss_get_hash_type()
336 core->mac[MRQC], in igb_rss_get_hash_type()
337 E1000_MRQC_EN_TCPIPV6EX(core->mac[MRQC]), in igb_rss_get_hash_type()
338 E1000_MRQC_EN_IPV6EX(core->mac[MRQC]), in igb_rss_get_hash_type()
339 E1000_MRQC_EN_IPV6(core->mac[MRQC])); in igb_rss_get_hash_type()
346 E1000_MRQC_EN_TCPIPV6EX(core->mac[MRQC])) { in igb_rss_get_hash_type()
351 (core->mac[MRQC] & E1000_MRQC_RSS_FIELD_IPV6_UDP)) { in igb_rss_get_hash_type()
355 if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) { in igb_rss_get_hash_type()
361 if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) { in igb_rss_get_hash_type()
404 return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]); in igb_rss_calc_hash()
435 info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash); in igb_rss_parse_packet()
442 if (core->mac[MRQC] & 1) { in igb_tx_insert_vlan()
445 if (core->mac[VMVIR0 + pool] & E1000_VMVIR_VLANA_DEFAULT) { in igb_tx_insert_vlan()
448 vlan = core->mac[VMVIR0 + pool] & 0xffff; in igb_tx_insert_vlan()
449 } else if (core->mac[VMVIR0 + pool] & E1000_VMVIR_VLANA_NEVER) { in igb_tx_insert_vlan()
456 core->mac[VET] & 0xffff); in igb_tx_insert_vlan()
472 e1000x_inc_reg_if_not_full(core->mac, TSCTC); in igb_setup_tx_offloads()
527 if (!(core->mac[MRQC] & 1)) { in igb_tx_pkt_switch()
532 if (!(core->mac[DTXSWC] & E1000_DTXSWC_VMDQ_LOOPBACK_EN)) { in igb_tx_pkt_switch()
559 ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) { in igb_tx_pkt_send()
575 e1000x_increase_size_stats(core->mac, PTCregs, tot_len); in igb_on_tx_done_update_stats()
576 e1000x_inc_reg_if_not_full(core->mac, TPT); in igb_on_tx_done_update_stats()
577 e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len); in igb_on_tx_done_update_stats()
581 e1000x_inc_reg_if_not_full(core->mac, BPTC); in igb_on_tx_done_update_stats()
584 e1000x_inc_reg_if_not_full(core->mac, MPTC); in igb_on_tx_done_update_stats()
592 e1000x_inc_reg_if_not_full(core->mac, GPTC); in igb_on_tx_done_update_stats()
593 e1000x_grow_8reg_if_not_full(core->mac, GOTCL, tot_len); in igb_on_tx_done_update_stats()
595 if (core->mac[MRQC] & 1) { in igb_on_tx_done_update_stats()
598 core->mac[PVFGOTC0 + (pool * 64)] += tot_len; in igb_on_tx_done_update_stats()
599 core->mac[PVFGPTC0 + (pool * 64)]++; in igb_on_tx_done_update_stats()
665 (core->mac[TSYNCTXCTL] & E1000_TSYNCTXCTL_ENABLED) && in igb_process_tx_desc()
666 !(core->mac[TSYNCTXCTL] & E1000_TSYNCTXCTL_VALID)) { in igb_process_tx_desc()
667 core->mac[TSYNCTXCTL] |= E1000_TSYNCTXCTL_VALID; in igb_process_tx_desc()
668 e1000x_timestamp(core->mac, core->timadj, TXSTMPL, TXSTMPH); in igb_process_tx_desc()
687 ent = (core->mac[IVAR0 + n / 4] >> (8 * (n % 4))) & 0xff; in igb_tx_wb_eic()
697 ent = (core->mac[IVAR0 + n / 4] >> (8 * (n % 4))) & 0xff; in igb_rx_wb_eic()
705 return core->mac[r->dh] == core->mac[r->dt] || in igb_ring_empty()
706 core->mac[r->dt] >= core->mac[r->dlen] / E1000_RING_DESC_LEN; in igb_ring_empty()
712 uint64_t bah = core->mac[r->dbah]; in igb_ring_base()
713 uint64_t bal = core->mac[r->dbal]; in igb_ring_base()
721 return igb_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh]; in igb_ring_head_descr()
727 core->mac[r->dh] += count; in igb_ring_advance()
729 if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) { in igb_ring_advance()
730 core->mac[r->dh] = 0; in igb_ring_advance()
737 trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen], in igb_ring_free_descr_num()
738 core->mac[r->dh], core->mac[r->dt]); in igb_ring_free_descr_num()
740 if (core->mac[r->dh] <= core->mac[r->dt]) { in igb_ring_free_descr_num()
741 return core->mac[r->dt] - core->mac[r->dh]; in igb_ring_free_descr_num()
744 if (core->mac[r->dh] > core->mac[r->dt]) { in igb_ring_free_descr_num()
745 return core->mac[r->dlen] / E1000_RING_DESC_LEN + in igb_ring_free_descr_num()
746 core->mac[r->dt] - core->mac[r->dh]; in igb_ring_free_descr_num()
756 return core->mac[r->dlen] > 0; in igb_ring_enabled()
838 tdwba = core->mac[E1000_TDWBAL(txi->idx) >> 2]; in igb_txdesc_writeback()
839 tdwba |= (uint64_t)core->mac[E1000_TDWBAH(txi->idx) >> 2] << 32; in igb_txdesc_writeback()
851 uint32_t buffer = cpu_to_le32(core->mac[txi->dh]); in igb_txdesc_writeback()
867 bool vmdq = core->mac[MRQC] & 1; in igb_tx_enabled()
871 return (core->mac[TCTL] & E1000_TCTL_EN) && in igb_tx_enabled()
872 (!vmdq || core->mac[VFTE] & BIT(pool)) && in igb_tx_enabled()
873 (core->mac[TXDCTL0 + (qn * 16)] & E1000_TXDCTL_QUEUE_ENABLE); in igb_tx_enabled()
919 uint32_t srrctl = core->mac[E1000_SRRCTL(r->idx) >> 2]; in igb_rxbufsize()
925 return e1000x_rxbufsize(core->mac[RCTL]); in igb_rxbufsize()
943 uint32_t srrctl = core->mac[E1000_SRRCTL(r->idx) >> 2]; in igb_rxhdrbufsize()
965 if (!e1000x_rx_ready(core->owner, core->mac)) { in igb_can_receive()
971 if (!(core->mac[RXDCTL0 + (i * 16)] & E1000_RXDCTL_QUEUE_ENABLE)) { in igb_can_receive()
1000 return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD); in igb_rx_l3_cso_enabled()
1006 return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD); in igb_rx_l4_cso_enabled()
1026 uint32_t f, ra[2], *macp, rctl = core->mac[RCTL]; in igb_receive_assign()
1042 if (core->mac[CTRL_EXT] & BIT(26)) { in igb_receive_assign()
1043 if (be16_to_cpu(ehdr->h_proto) == core->mac[VET] >> 16 && in igb_receive_assign()
1044 be16_to_cpu(l2_header->vlan[0].h_proto) == (core->mac[VET] & 0xffff)) { in igb_receive_assign()
1048 if (be16_to_cpu(ehdr->h_proto) == (core->mac[VET] & 0xffff)) { in igb_receive_assign()
1053 lpe = !!(core->mac[RCTL] & E1000_RCTL_LPE); in igb_receive_assign()
1054 rlpml = core->mac[RLPML]; in igb_receive_assign()
1055 if (!(core->mac[RCTL] & E1000_RCTL_SBP) && in igb_receive_assign()
1062 if ((core->mac[ETQF0 + *etqf] & E1000_ETQF_FILTER_ENABLE) && in igb_receive_assign()
1063 be16_to_cpu(ehdr->h_proto) == (core->mac[ETQF0 + *etqf] & E1000_ETQF_ETYPE_MASK)) { in igb_receive_assign()
1064 if ((core->mac[ETQF0 + *etqf] & E1000_ETQF_1588) && in igb_receive_assign()
1065 (core->mac[TSYNCRXCTL] & E1000_TSYNCRXCTL_ENABLED) && in igb_receive_assign()
1066 !(core->mac[TSYNCRXCTL] & E1000_TSYNCRXCTL_VALID) && in igb_receive_assign()
1069 ptp2.message_id_transport_specific == ((core->mac[TSYNCRXCFG] >> 8) & 255)) { in igb_receive_assign()
1070 e1000x_timestamp(core->mac, core->timadj, RXSTMPL, RXSTMPH); in igb_receive_assign()
1072 core->mac[TSYNCRXCTL] |= E1000_TSYNCRXCTL_VALID; in igb_receive_assign()
1073 core->mac[RXSATRL] = le32_to_cpu(ptp2.source_uuid_lo); in igb_receive_assign()
1074 core->mac[RXSATRH] = le16_to_cpu(ptp2.source_uuid_hi) | in igb_receive_assign()
1082 !e1000x_rx_vlan_filter(core->mac, l2_header->vlan + vlan_num - 1)) { in igb_receive_assign()
1086 if (core->mac[MRQC] & 1) { in igb_receive_assign()
1089 if (core->mac[VMOLR0 + i] & E1000_VMOLR_BAM) { in igb_receive_assign()
1094 for (macp = core->mac + RA; macp < core->mac + RA + 32; macp += 2) { in igb_receive_assign()
1105 for (macp = core->mac + RA2; macp < core->mac + RA2 + 16; macp += 2) { in igb_receive_assign()
1117 macp = core->mac + (is_multicast_ether_addr(ehdr->h_dest) ? MTA : UTA); in igb_receive_assign()
1123 if (core->mac[VMOLR0 + i] & E1000_VMOLR_ROMPE) { in igb_receive_assign()
1133 if (e1000x_vlan_rx_filter_enabled(core->mac)) { in igb_receive_assign()
1140 if ((core->mac[VLVF0 + i] & E1000_VLVF_VLANID_MASK) == vid && in igb_receive_assign()
1141 (core->mac[VLVF0 + i] & E1000_VLVF_VLANID_ENABLE)) { in igb_receive_assign()
1142 uint32_t poolsel = core->mac[VLVF0 + i] & E1000_VLVF_POOLSEL_MASK; in igb_receive_assign()
1148 if (core->mac[VMOLR0 + i] & E1000_VMOLR_AUPE) { in igb_receive_assign()
1158 !(core->mac[VT_CTL] & E1000_VT_CTL_DISABLE_DEF_POOL)) { in igb_receive_assign()
1159 uint32_t def_pl = core->mac[VT_CTL] & E1000_VT_CTL_DEFAULT_POOL_MASK; in igb_receive_assign()
1163 queues &= core->mac[VFRE]; in igb_receive_assign()
1166 lpe = !!(core->mac[VMOLR0 + i] & E1000_VMOLR_LPE); in igb_receive_assign()
1167 rlpml = core->mac[VMOLR0 + i] & E1000_VMOLR_RLPML_MASK; in igb_receive_assign()
1177 e1000x_inc_reg_if_not_full(core->mac, ROC); in igb_receive_assign()
1189 (core->mac[VMOLR0 + i] & E1000_VMOLR_RSSE)) { in igb_receive_assign()
1197 bool accepted = e1000x_rx_group_filter(core->mac, ehdr); in igb_receive_assign()
1199 for (macp = core->mac + RA2; macp < core->mac + RA2 + 16; macp += 2) { in igb_receive_assign()
1206 trace_e1000x_rx_flt_ucast_match((int)(macp - core->mac - RA2) / 2, in igb_receive_assign()
1374 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) { in igb_build_rx_metadata_common()
1466 if (hasip6 && !(core->mac[RFCTL] & E1000_RFCTL_IPV6_DIS)) { in igb_rx_desc_get_packet_type()
1517 if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) { in igb_write_adv_rx_descr()
1630 e1000x_update_rx_total_stats(core->mac, pkt_type, pkt_size, pkt_fcs_size); in igb_update_rx_stats()
1632 if (core->mac[MRQC] & 1) { in igb_update_rx_stats()
1635 core->mac[PVFGORC0 + (pool * 64)] += pkt_size + 4; in igb_update_rx_stats()
1636 core->mac[PVFGPRC0 + (pool * 64)]++; in igb_update_rx_stats()
1638 core->mac[PVFMPRC0 + (pool * 64)]++; in igb_update_rx_stats()
1647 ((core->mac[E1000_SRRCTL(rxi->idx) >> 2] >> 20) & 31) * 16; in igb_rx_descr_threshold_hit()
1687 if (fragment && (core->mac[RFCTL] & E1000_RFCTL_IPFRSP_DIS)) { in igb_do_ps()
1857 e1000x_fcs_len(core->mac)); in igb_write_payload_to_rx_buffers()
1909 pdma_st.total_size = pdma_st.size + e1000x_fcs_len(core->mac); in igb_write_packet_to_guest()
1959 if (core->mac[MRQC] & 1) { in igb_rx_strip_vlan()
1963 core->mac[RPLOLR] & E1000_RPLOLR_STRVLAN : in igb_rx_strip_vlan()
1964 core->mac[VMOLR0 + pool] & E1000_VMOLR_STRVLAN; in igb_rx_strip_vlan()
1967 return e1000x_vlan_enabled(core->mac); in igb_rx_strip_vlan()
2014 if (!e1000x_hw_rx_enabled(core->mac)) { in igb_receive_internal()
2033 e1000x_inc_reg_if_not_full(core->mac, RUC); in igb_receive_internal()
2057 !(core->mac[RXDCTL0 + (i * 16)] & E1000_RXDCTL_QUEUE_ENABLE)) { in igb_receive_internal()
2065 } else if (core->mac[CTRL_EXT] & BIT(26)) { in igb_receive_internal()
2073 core->mac[VET] & 0xffff, in igb_receive_internal()
2074 core->mac[VET] >> 16); in igb_receive_internal()
2077 e1000x_fcs_len(core->mac); in igb_receive_internal()
2117 core->mac[CTRL] |= E1000_CTRL_TFCE | E1000_CTRL_RFCE; in igb_update_flowctl_status()
2126 e1000x_update_regs_on_link_down(core->mac, core->phy); in igb_link_down()
2137 e1000x_restart_autoneg(core->mac, core->phy, core->autoneg_timer); in igb_set_phy_ctrl()
2144 uint32_t old_status = core->mac[STATUS]; in igb_core_set_link_status()
2149 e1000x_update_regs_on_link_down(core->mac, core->phy); in igb_core_set_link_status()
2153 e1000x_restart_autoneg(core->mac, core->phy, in igb_core_set_link_status()
2156 e1000x_update_regs_on_link_up(core->mac, core->phy); in igb_core_set_link_status()
2161 if (core->mac[STATUS] != old_status) { in igb_core_set_link_status()
2172 core->mac[CTRL] = val & ~E1000_CTRL_RST; in igb_set_ctrl()
2173 core->mac[CTRL_DUP] = core->mac[CTRL]; in igb_set_ctrl()
2190 core->mac[STATUS] |= E1000_STATUS_PHYRA; in igb_set_ctrl()
2211 core->mac[RFCTL] = val; in igb_set_rfctl()
2228 core->mac[RCTL] = val; in igb_set_rx_control()
2229 trace_e1000e_rx_set_rctl(core->mac[RCTL]); in igb_set_rx_control()
2251 if (timer->core->mac[timer->delay_reg] != 0) { in igb_postpone_interrupt()
2280 core->mac[ICR] &= ~E1000_ICR_ASSERTED; in igb_fix_icr_asserted()
2281 if (core->mac[ICR]) { in igb_fix_icr_asserted()
2282 core->mac[ICR] |= E1000_ICR_ASSERTED; in igb_fix_icr_asserted()
2285 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]); in igb_fix_icr_asserted()
2290 uint32_t old_causes = core->mac[ICR] & core->mac[IMS]; in igb_raise_interrupts()
2291 uint32_t old_ecauses = core->mac[EICR] & core->mac[EIMS]; in igb_raise_interrupts()
2297 core->mac[index], core->mac[index] | causes); in igb_raise_interrupts()
2299 core->mac[index] |= causes; in igb_raise_interrupts()
2301 if (core->mac[GPIE] & E1000_GPIE_MSIX_MODE) { in igb_raise_interrupts()
2302 raised_causes = core->mac[ICR] & core->mac[IMS] & ~old_causes; in igb_raise_interrupts()
2305 int_alloc = core->mac[IVAR_MISC] & 0xff; in igb_raise_interrupts()
2307 core->mac[EICR] |= BIT(int_alloc & 0x1f); in igb_raise_interrupts()
2312 int_alloc = (core->mac[IVAR_MISC] >> 8) & 0xff; in igb_raise_interrupts()
2314 core->mac[EICR] |= BIT(int_alloc & 0x1f); in igb_raise_interrupts()
2318 raised_ecauses = core->mac[EICR] & core->mac[EIMS] & ~old_ecauses; in igb_raise_interrupts()
2327 raised_causes = core->mac[ICR] & core->mac[IMS] & ~old_causes; in igb_raise_interrupts()
2332 core->mac[EICR] |= (raised_causes & E1000_ICR_DRSTA) | E1000_EICR_OTHER; in igb_raise_interrupts()
2349 core->mac[index], core->mac[index] & ~causes); in igb_lower_interrupts()
2351 core->mac[index] &= ~causes; in igb_lower_interrupts()
2353 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS], in igb_lower_interrupts()
2354 core->mac[ICR], core->mac[IMS]); in igb_lower_interrupts()
2356 if (!(core->mac[ICR] & core->mac[IMS]) && in igb_lower_interrupts()
2357 !(core->mac[GPIE] & E1000_GPIE_MSIX_MODE)) { in igb_lower_interrupts()
2358 core->mac[EICR] &= ~E1000_EICR_OTHER; in igb_lower_interrupts()
2368 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); in igb_set_eics()
2377 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); in igb_set_eims()
2386 uint32_t ent = core->mac[VTIVAR_MISC + vfn]; in mailbox_interrupt_to_vf()
2407 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_PFSTS; in igb_set_pfmailbox()
2412 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_PFACK; in igb_set_pfmailbox()
2418 if (!(core->mac[index] & E1000_P2VMAILBOX_VFU)) { in igb_set_pfmailbox()
2419 core->mac[index] |= E1000_P2VMAILBOX_PFU; in igb_set_pfmailbox()
2420 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_PFU; in igb_set_pfmailbox()
2423 core->mac[index] &= ~E1000_P2VMAILBOX_PFU; in igb_set_pfmailbox()
2424 core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_PFU; in igb_set_pfmailbox()
2428 core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_VFU; in igb_set_pfmailbox()
2429 core->mac[MBVFICR] &= ~((E1000_MBVFICR_VFACK_VF1 << vfn) | in igb_set_pfmailbox()
2441 core->mac[MBVFICR] |= E1000_MBVFICR_VFREQ_VF1 << vfn; in igb_set_vfmailbox()
2446 core->mac[MBVFICR] |= E1000_MBVFICR_VFACK_VF1 << vfn; in igb_set_vfmailbox()
2452 if (!(core->mac[index] & E1000_V2PMAILBOX_PFU)) { in igb_set_vfmailbox()
2453 core->mac[index] |= E1000_V2PMAILBOX_VFU; in igb_set_vfmailbox()
2454 core->mac[P2VMAILBOX0 + vfn] |= E1000_P2VMAILBOX_VFU; in igb_set_vfmailbox()
2457 core->mac[index] &= ~E1000_V2PMAILBOX_VFU; in igb_set_vfmailbox()
2458 core->mac[P2VMAILBOX0 + vfn] &= ~E1000_P2VMAILBOX_VFU; in igb_set_vfmailbox()
2470 core->mac[RXDCTL0 + (qn0 * 16)] &= ~E1000_RXDCTL_QUEUE_ENABLE; in igb_core_vf_reset()
2471 core->mac[RXDCTL0 + (qn1 * 16)] &= ~E1000_RXDCTL_QUEUE_ENABLE; in igb_core_vf_reset()
2472 core->mac[TXDCTL0 + (qn0 * 16)] &= ~E1000_TXDCTL_QUEUE_ENABLE; in igb_core_vf_reset()
2473 core->mac[TXDCTL0 + (qn1 * 16)] &= ~E1000_TXDCTL_QUEUE_ENABLE; in igb_core_vf_reset()
2474 core->mac[VFRE] &= ~BIT(vfn); in igb_core_vf_reset()
2475 core->mac[VFTE] &= ~BIT(vfn); in igb_core_vf_reset()
2477 core->mac[VFLRE] |= BIT(vfn); in igb_core_vf_reset()
2484 core->mac[index] &= ~val; in igb_w1c()
2489 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); in igb_set_eimc()
2500 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); in igb_set_eiac()
2509 core->mac[EIAC] |= (val & E1000_EICR_MSIX_MASK); in igb_set_eiac()
2515 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); in igb_set_eiam()
2521 core->mac[EIAM] |= in igb_set_eiam()
2529 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); in igb_set_eicr()
2555 core->mac[index] = val; in igb_set_vteics()
2563 core->mac[index] = val; in igb_set_vteims()
2571 core->mac[index] = val; in igb_set_vteimc()
2579 core->mac[index] = val; in igb_set_vteiac()
2587 core->mac[index] = val; in igb_set_vteiam()
2595 core->mac[index] = val; in igb_set_vteicr()
2606 core->mac[index] = val; in igb_set_vtivar()
2612 core->mac[IVAR0 + n / 4] |= ent << 8 * (n % 4); in igb_set_vtivar()
2620 core->mac[IVAR0 + n / 4] |= ent << 8 * (n % 4); in igb_set_vtivar()
2633 e1000x_update_regs_on_autoneg_done(core->mac, core->phy); in igb_autoneg_timer()
2690 val = core->mac[MDIC] | E1000_MDIC_ERROR; in igb_set_mdic()
2708 core->mac[MDIC] = val | E1000_MDIC_READY; in igb_set_mdic()
2718 core->mac[index] = val & 0xffff; in igb_set_rdt()
2727 core->mac[index] &= ~E1000_STATUS_PHYRA; in igb_set_status()
2740 core->mac[CTRL_EXT] = val; in igb_set_ctrlext()
2742 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PFRSTD) { in igb_set_ctrlext()
2744 core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_RSTI; in igb_set_ctrlext()
2745 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_RSTD; in igb_set_ctrlext()
2755 core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK; in igb_set_pbaclr()
2762 if (core->mac[PBACLR] & BIT(i)) { in igb_set_pbaclr()
2771 core->mac[FCRTH] = val & 0xFFF8; in igb_set_fcrth()
2777 core->mac[FCRTL] = val & 0x8000FFF8; in igb_set_fcrtl()
2784 core->mac[index] = val & (BIT(num) - 1); \
2794 core->mac[index] = val & 0xffff0; in igb_set_dlen()
2800 core->mac[index] = val & E1000_XDBAL_MASK; in igb_set_dbal()
2809 core->mac[index] = val & 0xffff; in igb_set_tdt()
2842 if ((core->mac[GPIE] & E1000_GPIE_NSICR) || in igb_nsicr()
2843 (core->mac[IMS] && (core->mac[ICR] & E1000_ICR_INT_ASSERTED))) { in igb_nsicr()
2844 igb_lower_interrupts(core, IMS, core->mac[IAM]); in igb_nsicr()
2857 return core->mac[index]; in igb_mac_readreg()
2863 trace_e1000e_irq_read_ics(core->mac[ICS]); in igb_mac_ics_read()
2864 return core->mac[ICS]; in igb_mac_ics_read()
2870 trace_e1000e_irq_read_ims(core->mac[IMS]); in igb_mac_ims_read()
2871 return core->mac[IMS]; in igb_mac_ims_read()
2877 uint32_t val = core->mac[SWSM]; in igb_mac_swsm_read()
2878 core->mac[SWSM] = val | E1000_SWSM_SMBI; in igb_mac_swsm_read()
2890 uint32_t val = core->mac[index]; in igb_mac_vfmailbox_read()
2892 core->mac[index] &= ~(E1000_V2PMAILBOX_PFSTS | E1000_V2PMAILBOX_PFACK | in igb_mac_vfmailbox_read()
2901 uint32_t ret = core->mac[ICR]; in igb_mac_icr_read()
2903 if (core->mac[GPIE] & E1000_GPIE_NSICR) { in igb_mac_icr_read()
2906 } else if (core->mac[IMS] == 0) { in igb_mac_icr_read()
2909 } else if (core->mac[ICR] & E1000_ICR_INT_ASSERTED) { in igb_mac_icr_read()
2923 uint32_t ret = core->mac[index]; in igb_mac_read_clr4()
2925 core->mac[index] = 0; in igb_mac_read_clr4()
2932 uint32_t ret = core->mac[index]; in igb_mac_read_clr8()
2934 core->mac[index] = 0; in igb_mac_read_clr8()
2935 core->mac[index - 1] = 0; in igb_mac_read_clr8()
2942 uint32_t val = core->mac[CTRL]; in igb_get_ctrl()
2957 uint32_t res = core->mac[STATUS]; in igb_get_status()
2960 if (core->mac[CTRL] & E1000_CTRL_FRCDPX) { in igb_get_status()
2961 res |= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0; in igb_get_status()
2966 if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) || in igb_get_status()
2967 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) { in igb_get_status()
2968 switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) { in igb_get_status()
2989 if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE)) { in igb_get_status()
2999 core->mac[index] = val; in igb_mac_writereg()
3007 core->mac[index] = val; in igb_mac_setmacaddr()
3009 macaddr[0] = cpu_to_le32(core->mac[RA]); in igb_mac_setmacaddr()
3010 macaddr[1] = cpu_to_le32(core->mac[RA + 1]); in igb_mac_setmacaddr()
3024 core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits); in igb_set_eecd()
3039 core->mac[EERD] = flags | in igb_set_eerd()
3052 core->mac[index] = val & 0x7FFE; in igb_set_eitr()
3071 core->mac[RXCSUM] = val; in igb_set_rxcsum()
3078 uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS; in igb_set_gcr()
3079 core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits; in igb_set_gcr()
3084 e1000x_timestamp(core->mac, core->timadj, SYSTIML, SYSTIMH); in igb_get_systiml()
3085 return core->mac[SYSTIML]; in igb_get_systiml()
3090 core->mac[TSYNCRXCTL] &= ~E1000_TSYNCRXCTL_VALID; in igb_get_rxsatrh()
3091 return core->mac[RXSATRH]; in igb_get_rxsatrh()
3096 core->mac[TSYNCTXCTL] &= ~E1000_TSYNCTXCTL_VALID; in igb_get_txstmph()
3097 return core->mac[TXSTMPH]; in igb_get_txstmph()
3102 e1000x_set_timinca(core->mac, &core->timadj, val); in igb_set_timinca()
3107 core->mac[TIMADJH] = val; in igb_set_timadjh()
3108 core->timadj += core->mac[TIMADJL] | ((int64_t)core->mac[TIMADJH] << 32); in igb_set_timadjh()
4483 core->mac[i] = i < ARRAY_SIZE(igb_mac_reg_init) ? in igb_reset()
4491 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac); in igb_reset()
4495 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_RSTI; in igb_reset()
4543 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0; in igb_core_post_load()