Lines Matching full:core
2 * Core code for QEMU e1000e emulation
66 e1000e_receive_internal(E1000ECore *core, const struct iovec *iov, int iovcnt,
70 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val);
72 static void e1000e_reset(E1000ECore *core, bool sw);
75 e1000e_process_ts_option(E1000ECore *core, struct e1000_tx_desc *dp) in e1000e_process_ts_option() argument
83 e1000e_process_snap_option(E1000ECore *core, uint32_t cmd_and_length) in e1000e_process_snap_option() argument
91 e1000e_raise_legacy_irq(E1000ECore *core) in e1000e_raise_legacy_irq() argument
94 e1000x_inc_reg_if_not_full(core->mac, IAC); in e1000e_raise_legacy_irq()
95 pci_set_irq(core->owner, 1); in e1000e_raise_legacy_irq()
99 e1000e_lower_legacy_irq(E1000ECore *core) in e1000e_lower_legacy_irq() argument
102 pci_set_irq(core->owner, 0); in e1000e_lower_legacy_irq()
108 int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] * in e1000e_intrmgr_rearm_timer()
136 e1000e_intrmgr_fire_delayed_interrupts(E1000ECore *core) in e1000e_intrmgr_fire_delayed_interrupts() argument
139 e1000e_set_interrupt_cause(core, 0); in e1000e_intrmgr_fire_delayed_interrupts()
150 e1000e_intrmgr_fire_delayed_interrupts(timer->core); in e1000e_intrmgr_on_timer()
160 if (timer->core->mac[IMS] & timer->core->mac[ICR]) { in e1000e_intrmgr_on_throttling_timer()
161 if (msi_enabled(timer->core->owner)) { in e1000e_intrmgr_on_throttling_timer()
163 msi_notify(timer->core->owner, 0); in e1000e_intrmgr_on_throttling_timer()
166 e1000e_raise_legacy_irq(timer->core); in e1000e_intrmgr_on_throttling_timer()
175 int idx = timer - &timer->core->eitr[0]; in e1000e_intrmgr_on_msix_throttling_timer()
180 msix_notify(timer->core->owner, idx); in e1000e_intrmgr_on_msix_throttling_timer()
184 e1000e_intrmgr_initialize_all_timers(E1000ECore *core, bool create) in e1000e_intrmgr_initialize_all_timers() argument
188 core->radv.delay_reg = RADV; in e1000e_intrmgr_initialize_all_timers()
189 core->rdtr.delay_reg = RDTR; in e1000e_intrmgr_initialize_all_timers()
190 core->raid.delay_reg = RAID; in e1000e_intrmgr_initialize_all_timers()
191 core->tadv.delay_reg = TADV; in e1000e_intrmgr_initialize_all_timers()
192 core->tidv.delay_reg = TIDV; in e1000e_intrmgr_initialize_all_timers()
194 core->radv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; in e1000e_intrmgr_initialize_all_timers()
195 core->rdtr.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; in e1000e_intrmgr_initialize_all_timers()
196 core->raid.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; in e1000e_intrmgr_initialize_all_timers()
197 core->tadv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; in e1000e_intrmgr_initialize_all_timers()
198 core->tidv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; in e1000e_intrmgr_initialize_all_timers()
200 core->radv.core = core; in e1000e_intrmgr_initialize_all_timers()
201 core->rdtr.core = core; in e1000e_intrmgr_initialize_all_timers()
202 core->raid.core = core; in e1000e_intrmgr_initialize_all_timers()
203 core->tadv.core = core; in e1000e_intrmgr_initialize_all_timers()
204 core->tidv.core = core; in e1000e_intrmgr_initialize_all_timers()
206 core->itr.core = core; in e1000e_intrmgr_initialize_all_timers()
207 core->itr.delay_reg = ITR; in e1000e_intrmgr_initialize_all_timers()
208 core->itr.delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES; in e1000e_intrmgr_initialize_all_timers()
211 core->eitr[i].core = core; in e1000e_intrmgr_initialize_all_timers()
212 core->eitr[i].delay_reg = EITR + i; in e1000e_intrmgr_initialize_all_timers()
213 core->eitr[i].delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES; in e1000e_intrmgr_initialize_all_timers()
220 core->radv.timer = in e1000e_intrmgr_initialize_all_timers()
221 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->radv); in e1000e_intrmgr_initialize_all_timers()
222 core->rdtr.timer = in e1000e_intrmgr_initialize_all_timers()
223 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->rdtr); in e1000e_intrmgr_initialize_all_timers()
224 core->raid.timer = in e1000e_intrmgr_initialize_all_timers()
225 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->raid); in e1000e_intrmgr_initialize_all_timers()
227 core->tadv.timer = in e1000e_intrmgr_initialize_all_timers()
228 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tadv); in e1000e_intrmgr_initialize_all_timers()
229 core->tidv.timer = in e1000e_intrmgr_initialize_all_timers()
230 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tidv); in e1000e_intrmgr_initialize_all_timers()
232 core->itr.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, in e1000e_intrmgr_initialize_all_timers()
234 &core->itr); in e1000e_intrmgr_initialize_all_timers()
237 core->eitr[i].timer = in e1000e_intrmgr_initialize_all_timers()
240 &core->eitr[i]); in e1000e_intrmgr_initialize_all_timers()
245 e1000e_intrmgr_stop_delay_timers(E1000ECore *core) in e1000e_intrmgr_stop_delay_timers() argument
247 e1000e_intrmgr_stop_timer(&core->radv); in e1000e_intrmgr_stop_delay_timers()
248 e1000e_intrmgr_stop_timer(&core->rdtr); in e1000e_intrmgr_stop_delay_timers()
249 e1000e_intrmgr_stop_timer(&core->raid); in e1000e_intrmgr_stop_delay_timers()
250 e1000e_intrmgr_stop_timer(&core->tidv); in e1000e_intrmgr_stop_delay_timers()
251 e1000e_intrmgr_stop_timer(&core->tadv); in e1000e_intrmgr_stop_delay_timers()
255 e1000e_intrmgr_delay_rx_causes(E1000ECore *core, uint32_t *causes) in e1000e_intrmgr_delay_rx_causes() argument
258 uint32_t rdtr = core->mac[RDTR]; in e1000e_intrmgr_delay_rx_causes()
259 uint32_t radv = core->mac[RADV]; in e1000e_intrmgr_delay_rx_causes()
260 uint32_t raid = core->mac[RAID]; in e1000e_intrmgr_delay_rx_causes()
262 if (msix_enabled(core->owner)) { in e1000e_intrmgr_delay_rx_causes()
270 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS)) { in e1000e_intrmgr_delay_rx_causes()
275 core->delayed_causes |= *causes & delayable_causes; in e1000e_intrmgr_delay_rx_causes()
290 if ((raid == 0) && (core->delayed_causes & E1000_ICR_ACK)) { in e1000e_intrmgr_delay_rx_causes()
295 e1000e_intrmgr_rearm_timer(&core->rdtr); in e1000e_intrmgr_delay_rx_causes()
297 if (!core->radv.running && (radv != 0)) { in e1000e_intrmgr_delay_rx_causes()
298 e1000e_intrmgr_rearm_timer(&core->radv); in e1000e_intrmgr_delay_rx_causes()
301 if (!core->raid.running && (core->delayed_causes & E1000_ICR_ACK)) { in e1000e_intrmgr_delay_rx_causes()
302 e1000e_intrmgr_rearm_timer(&core->raid); in e1000e_intrmgr_delay_rx_causes()
309 e1000e_intrmgr_delay_tx_causes(E1000ECore *core, uint32_t *causes) in e1000e_intrmgr_delay_tx_causes() argument
316 if (msix_enabled(core->owner)) { in e1000e_intrmgr_delay_tx_causes()
321 core->delayed_causes |= *causes & delayable_causes; in e1000e_intrmgr_delay_tx_causes()
330 e1000e_intrmgr_rearm_timer(&core->tidv); in e1000e_intrmgr_delay_tx_causes()
332 if (!core->tadv.running && (core->mac[TADV] != 0)) { in e1000e_intrmgr_delay_tx_causes()
333 e1000e_intrmgr_rearm_timer(&core->tadv); in e1000e_intrmgr_delay_tx_causes()
340 e1000e_intmgr_collect_delayed_causes(E1000ECore *core) in e1000e_intmgr_collect_delayed_causes() argument
344 if (msix_enabled(core->owner)) { in e1000e_intmgr_collect_delayed_causes()
345 assert(core->delayed_causes == 0); in e1000e_intmgr_collect_delayed_causes()
349 res = core->delayed_causes; in e1000e_intmgr_collect_delayed_causes()
350 core->delayed_causes = 0; in e1000e_intmgr_collect_delayed_causes()
352 e1000e_intrmgr_stop_delay_timers(core); in e1000e_intmgr_collect_delayed_causes()
358 e1000e_intrmgr_fire_all_timers(E1000ECore *core) in e1000e_intrmgr_fire_all_timers() argument
362 if (core->itr.running) { in e1000e_intrmgr_fire_all_timers()
363 timer_del(core->itr.timer); in e1000e_intrmgr_fire_all_timers()
364 e1000e_intrmgr_on_throttling_timer(&core->itr); in e1000e_intrmgr_fire_all_timers()
368 if (core->eitr[i].running) { in e1000e_intrmgr_fire_all_timers()
369 timer_del(core->eitr[i].timer); in e1000e_intrmgr_fire_all_timers()
370 e1000e_intrmgr_on_msix_throttling_timer(&core->eitr[i]); in e1000e_intrmgr_fire_all_timers()
376 e1000e_intrmgr_resume(E1000ECore *core) in e1000e_intrmgr_resume() argument
380 e1000e_intmgr_timer_resume(&core->radv); in e1000e_intrmgr_resume()
381 e1000e_intmgr_timer_resume(&core->rdtr); in e1000e_intrmgr_resume()
382 e1000e_intmgr_timer_resume(&core->raid); in e1000e_intrmgr_resume()
383 e1000e_intmgr_timer_resume(&core->tidv); in e1000e_intrmgr_resume()
384 e1000e_intmgr_timer_resume(&core->tadv); in e1000e_intrmgr_resume()
386 e1000e_intmgr_timer_resume(&core->itr); in e1000e_intrmgr_resume()
389 e1000e_intmgr_timer_resume(&core->eitr[i]); in e1000e_intrmgr_resume()
394 e1000e_intrmgr_reset(E1000ECore *core) in e1000e_intrmgr_reset() argument
398 core->delayed_causes = 0; in e1000e_intrmgr_reset()
400 e1000e_intrmgr_stop_delay_timers(core); in e1000e_intrmgr_reset()
402 e1000e_intrmgr_stop_timer(&core->itr); in e1000e_intrmgr_reset()
405 e1000e_intrmgr_stop_timer(&core->eitr[i]); in e1000e_intrmgr_reset()
410 e1000e_intrmgr_pci_unint(E1000ECore *core) in e1000e_intrmgr_pci_unint() argument
414 timer_free(core->radv.timer); in e1000e_intrmgr_pci_unint()
415 timer_free(core->rdtr.timer); in e1000e_intrmgr_pci_unint()
416 timer_free(core->raid.timer); in e1000e_intrmgr_pci_unint()
418 timer_free(core->tadv.timer); in e1000e_intrmgr_pci_unint()
419 timer_free(core->tidv.timer); in e1000e_intrmgr_pci_unint()
421 timer_free(core->itr.timer); in e1000e_intrmgr_pci_unint()
424 timer_free(core->eitr[i].timer); in e1000e_intrmgr_pci_unint()
429 e1000e_intrmgr_pci_realize(E1000ECore *core) in e1000e_intrmgr_pci_realize() argument
431 e1000e_intrmgr_initialize_all_timers(core, true); in e1000e_intrmgr_pci_realize()
435 e1000e_rx_csum_enabled(E1000ECore *core) in e1000e_rx_csum_enabled() argument
437 return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true; in e1000e_rx_csum_enabled()
441 e1000e_rx_use_legacy_descriptor(E1000ECore *core) in e1000e_rx_use_legacy_descriptor() argument
443 return (core->mac[RFCTL] & E1000_RFCTL_EXTEN) ? false : true; in e1000e_rx_use_legacy_descriptor()
447 e1000e_rx_use_ps_descriptor(E1000ECore *core) in e1000e_rx_use_ps_descriptor() argument
449 return !e1000e_rx_use_legacy_descriptor(core) && in e1000e_rx_use_ps_descriptor()
450 (core->mac[RCTL] & E1000_RCTL_DTYP_PS); in e1000e_rx_use_ps_descriptor()
454 e1000e_rss_enabled(E1000ECore *core) in e1000e_rss_enabled() argument
456 return E1000_MRQC_ENABLED(core->mac[MRQC]) && in e1000e_rss_enabled()
457 !e1000e_rx_csum_enabled(core) && in e1000e_rss_enabled()
458 !e1000e_rx_use_legacy_descriptor(core); in e1000e_rss_enabled()
469 e1000e_rss_get_hash_type(E1000ECore *core, struct NetRxPkt *pkt) in e1000e_rss_get_hash_type() argument
474 assert(e1000e_rss_enabled(core)); in e1000e_rss_get_hash_type()
479 trace_e1000e_rx_rss_ip4(l4hdr_proto, core->mac[MRQC], in e1000e_rss_get_hash_type()
480 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]), in e1000e_rss_get_hash_type()
481 E1000_MRQC_EN_IPV4(core->mac[MRQC])); in e1000e_rss_get_hash_type()
484 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) { in e1000e_rss_get_hash_type()
488 if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) { in e1000e_rss_get_hash_type()
494 bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS; in e1000e_rss_get_hash_type()
495 bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS; in e1000e_rss_get_hash_type()
504 trace_e1000e_rx_rss_ip6_rfctl(core->mac[RFCTL]); in e1000e_rss_get_hash_type()
509 core->mac[MRQC], in e1000e_rss_get_hash_type()
510 E1000_MRQC_EN_TCPIPV6EX(core->mac[MRQC]), in e1000e_rss_get_hash_type()
511 E1000_MRQC_EN_IPV6EX(core->mac[MRQC]), in e1000e_rss_get_hash_type()
512 E1000_MRQC_EN_IPV6(core->mac[MRQC])); in e1000e_rss_get_hash_type()
519 E1000_MRQC_EN_TCPIPV6EX(core->mac[MRQC])) { in e1000e_rss_get_hash_type()
523 if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) { in e1000e_rss_get_hash_type()
529 if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) { in e1000e_rss_get_hash_type()
539 e1000e_rss_calc_hash(E1000ECore *core, in e1000e_rss_calc_hash() argument
545 assert(e1000e_rss_enabled(core)); in e1000e_rss_calc_hash()
567 return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]); in e1000e_rss_calc_hash()
571 e1000e_rss_parse_packet(E1000ECore *core, in e1000e_rss_parse_packet() argument
577 if (!e1000e_rss_enabled(core)) { in e1000e_rss_parse_packet()
588 info->type = e1000e_rss_get_hash_type(core, pkt); in e1000e_rss_parse_packet()
598 info->hash = e1000e_rss_calc_hash(core, pkt, info); in e1000e_rss_parse_packet()
599 info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash); in e1000e_rss_parse_packet()
603 e1000e_setup_tx_offloads(E1000ECore *core, struct e1000e_tx *tx) in e1000e_setup_tx_offloads() argument
611 e1000x_inc_reg_if_not_full(core->mac, TSCTC); in e1000e_setup_tx_offloads()
628 static void e1000e_tx_pkt_callback(void *core, in e1000e_tx_pkt_callback() argument
634 e1000e_receive_internal(core, virt_iov, virt_iovcnt, true); in e1000e_tx_pkt_callback()
638 e1000e_tx_pkt_send(E1000ECore *core, struct e1000e_tx *tx, int queue_index) in e1000e_tx_pkt_send() argument
640 int target_queue = MIN(core->max_queue_num, queue_index); in e1000e_tx_pkt_send()
641 NetClientState *queue = qemu_get_subqueue(core->owner_nic, target_queue); in e1000e_tx_pkt_send()
643 if (!e1000e_setup_tx_offloads(core, tx)) { in e1000e_tx_pkt_send()
649 if ((core->phy[0][MII_BMCR] & MII_BMCR_LOOPBACK) || in e1000e_tx_pkt_send()
650 ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) { in e1000e_tx_pkt_send()
652 e1000e_tx_pkt_callback, core); in e1000e_tx_pkt_send()
659 e1000e_on_tx_done_update_stats(E1000ECore *core, struct NetTxPkt *tx_pkt) in e1000e_on_tx_done_update_stats() argument
666 e1000x_increase_size_stats(core->mac, PTCregs, tot_len); in e1000e_on_tx_done_update_stats()
667 e1000x_inc_reg_if_not_full(core->mac, TPT); in e1000e_on_tx_done_update_stats()
668 e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len); in e1000e_on_tx_done_update_stats()
672 e1000x_inc_reg_if_not_full(core->mac, BPTC); in e1000e_on_tx_done_update_stats()
675 e1000x_inc_reg_if_not_full(core->mac, MPTC); in e1000e_on_tx_done_update_stats()
683 e1000x_inc_reg_if_not_full(core->mac, GPTC); in e1000e_on_tx_done_update_stats()
684 e1000x_grow_8reg_if_not_full(core->mac, GOTCL, tot_len); in e1000e_on_tx_done_update_stats()
688 e1000e_process_tx_desc(E1000ECore *core, in e1000e_process_tx_desc() argument
702 e1000e_process_snap_option(core, le32_to_cpu(xp->cmd_and_length)); in e1000e_process_tx_desc()
708 e1000e_process_ts_option(core, dp); in e1000e_process_tx_desc()
711 e1000e_process_ts_option(core, dp); in e1000e_process_tx_desc()
718 if (!net_tx_pkt_add_raw_fragment_pci(tx->tx_pkt, core->owner, in e1000e_process_tx_desc()
726 if (e1000x_vlan_enabled(core->mac) && in e1000e_process_tx_desc()
729 le16_to_cpu(dp->upper.fields.special), core->mac[VET]); in e1000e_process_tx_desc()
731 if (e1000e_tx_pkt_send(core, tx, queue_index)) { in e1000e_process_tx_desc()
732 e1000e_on_tx_done_update_stats(core, tx->tx_pkt); in e1000e_process_tx_desc()
737 net_tx_pkt_reset(tx->tx_pkt, net_tx_pkt_unmap_frag_pci, core->owner); in e1000e_process_tx_desc()
745 e1000e_tx_wb_interrupt_cause(E1000ECore *core, int queue_idx) in e1000e_tx_wb_interrupt_cause() argument
747 if (!msix_enabled(core->owner)) { in e1000e_tx_wb_interrupt_cause()
755 e1000e_rx_wb_interrupt_cause(E1000ECore *core, int queue_idx, in e1000e_rx_wb_interrupt_cause() argument
758 if (!msix_enabled(core->owner)) { in e1000e_rx_wb_interrupt_cause()
766 e1000e_txdesc_writeback(E1000ECore *core, dma_addr_t base, in e1000e_txdesc_writeback() argument
772 !(core->mac[IVAR] & E1000_IVAR_TX_INT_EVERY_WB)) { in e1000e_txdesc_writeback()
781 pci_dma_write(core->owner, base + ((char *)&dp->upper - (char *)dp), in e1000e_txdesc_writeback()
783 return e1000e_tx_wb_interrupt_cause(core, queue_idx); in e1000e_txdesc_writeback()
796 e1000e_ring_empty(E1000ECore *core, const E1000ERingInfo *r) in e1000e_ring_empty() argument
798 return core->mac[r->dh] == core->mac[r->dt] || in e1000e_ring_empty()
799 core->mac[r->dt] >= core->mac[r->dlen] / E1000_RING_DESC_LEN; in e1000e_ring_empty()
803 e1000e_ring_base(E1000ECore *core, const E1000ERingInfo *r) in e1000e_ring_base() argument
805 uint64_t bah = core->mac[r->dbah]; in e1000e_ring_base()
806 uint64_t bal = core->mac[r->dbal]; in e1000e_ring_base()
812 e1000e_ring_head_descr(E1000ECore *core, const E1000ERingInfo *r) in e1000e_ring_head_descr() argument
814 return e1000e_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh]; in e1000e_ring_head_descr()
818 e1000e_ring_advance(E1000ECore *core, const E1000ERingInfo *r, uint32_t count) in e1000e_ring_advance() argument
820 core->mac[r->dh] += count; in e1000e_ring_advance()
822 if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) { in e1000e_ring_advance()
823 core->mac[r->dh] = 0; in e1000e_ring_advance()
828 e1000e_ring_free_descr_num(E1000ECore *core, const E1000ERingInfo *r) in e1000e_ring_free_descr_num() argument
830 trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen], in e1000e_ring_free_descr_num()
831 core->mac[r->dh], core->mac[r->dt]); in e1000e_ring_free_descr_num()
833 if (core->mac[r->dh] <= core->mac[r->dt]) { in e1000e_ring_free_descr_num()
834 return core->mac[r->dt] - core->mac[r->dh]; in e1000e_ring_free_descr_num()
837 if (core->mac[r->dh] > core->mac[r->dt]) { in e1000e_ring_free_descr_num()
838 return core->mac[r->dlen] / E1000_RING_DESC_LEN + in e1000e_ring_free_descr_num()
839 core->mac[r->dt] - core->mac[r->dh]; in e1000e_ring_free_descr_num()
846 e1000e_ring_enabled(E1000ECore *core, const E1000ERingInfo *r) in e1000e_ring_enabled() argument
848 return core->mac[r->dlen] > 0; in e1000e_ring_enabled()
852 e1000e_ring_len(E1000ECore *core, const E1000ERingInfo *r) in e1000e_ring_len() argument
854 return core->mac[r->dlen]; in e1000e_ring_len()
869 e1000e_tx_ring_init(E1000ECore *core, E1000E_TxRing *txr, int idx) in e1000e_tx_ring_init() argument
879 txr->tx = &core->tx[idx]; in e1000e_tx_ring_init()
887 e1000e_rx_ring_init(E1000ECore *core, E1000E_RxRing *rxr, int idx) in e1000e_rx_ring_init() argument
900 e1000e_start_xmit(E1000ECore *core, const E1000E_TxRing *txr) in e1000e_start_xmit() argument
908 if (!(core->mac[TCTL] & E1000_TCTL_EN)) { in e1000e_start_xmit()
913 while (!e1000e_ring_empty(core, txi)) { in e1000e_start_xmit()
914 base = e1000e_ring_head_descr(core, txi); in e1000e_start_xmit()
916 pci_dma_read(core->owner, base, &desc, sizeof(desc)); in e1000e_start_xmit()
921 e1000e_process_tx_desc(core, txr->tx, &desc, txi->idx); in e1000e_start_xmit()
922 cause |= e1000e_txdesc_writeback(core, base, &desc, &ide, txi->idx); in e1000e_start_xmit()
924 e1000e_ring_advance(core, txi, 1); in e1000e_start_xmit()
927 if (!ide || !e1000e_intrmgr_delay_tx_causes(core, &cause)) { in e1000e_start_xmit()
928 e1000e_set_interrupt_cause(core, cause); in e1000e_start_xmit()
931 net_tx_pkt_reset(txr->tx->tx_pkt, net_tx_pkt_unmap_frag_pci, core->owner); in e1000e_start_xmit()
935 e1000e_has_rxbufs(E1000ECore *core, const E1000ERingInfo *r, in e1000e_has_rxbufs() argument
938 uint32_t bufs = e1000e_ring_free_descr_num(core, r); in e1000e_has_rxbufs()
941 core->rx_desc_buf_size); in e1000e_has_rxbufs()
943 return total_size <= bufs / (core->rx_desc_len / E1000_MIN_RX_DESC_LEN) * in e1000e_has_rxbufs()
944 core->rx_desc_buf_size; in e1000e_has_rxbufs()
948 e1000e_start_recv(E1000ECore *core) in e1000e_start_recv() argument
954 for (i = 0; i <= core->max_queue_num; i++) { in e1000e_start_recv()
955 qemu_flush_queued_packets(qemu_get_subqueue(core->owner_nic, i)); in e1000e_start_recv()
960 e1000e_can_receive(E1000ECore *core) in e1000e_can_receive() argument
964 if (!e1000x_rx_ready(core->owner, core->mac)) { in e1000e_can_receive()
971 e1000e_rx_ring_init(core, &rxr, i); in e1000e_can_receive()
972 if (e1000e_ring_enabled(core, rxr.i) && in e1000e_can_receive()
973 e1000e_has_rxbufs(core, rxr.i, 1)) { in e1000e_can_receive()
984 e1000e_receive(E1000ECore *core, const uint8_t *buf, size_t size) in e1000e_receive() argument
991 return e1000e_receive_iov(core, &iov, 1); in e1000e_receive()
995 e1000e_rx_l3_cso_enabled(E1000ECore *core) in e1000e_rx_l3_cso_enabled() argument
997 return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD); in e1000e_rx_l3_cso_enabled()
1001 e1000e_rx_l4_cso_enabled(E1000ECore *core) in e1000e_rx_l4_cso_enabled() argument
1003 return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD); in e1000e_rx_l4_cso_enabled()
1007 e1000e_receive_filter(E1000ECore *core, const void *buf) in e1000e_receive_filter() argument
1009 return (!e1000x_is_vlan_packet(buf, core->mac[VET]) || in e1000e_receive_filter()
1010 e1000x_rx_vlan_filter(core->mac, PKT_GET_VLAN_HDR(buf))) && in e1000e_receive_filter()
1011 e1000x_rx_group_filter(core->mac, buf); in e1000e_receive_filter()
1015 e1000e_read_lgcy_rx_descr(E1000ECore *core, struct e1000_rx_desc *desc, in e1000e_read_lgcy_rx_descr() argument
1022 e1000e_read_ext_rx_descr(E1000ECore *core, union e1000_rx_desc_extended *desc, in e1000e_read_ext_rx_descr() argument
1029 e1000e_read_ps_rx_descr(E1000ECore *core, in e1000e_read_ps_rx_descr() argument
1044 e1000e_read_rx_descr(E1000ECore *core, union e1000_rx_desc_union *desc, in e1000e_read_rx_descr() argument
1047 if (e1000e_rx_use_legacy_descriptor(core)) { in e1000e_read_rx_descr()
1048 e1000e_read_lgcy_rx_descr(core, &desc->legacy, &buff_addr[0]); in e1000e_read_rx_descr()
1051 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { in e1000e_read_rx_descr()
1052 e1000e_read_ps_rx_descr(core, &desc->packet_split, buff_addr); in e1000e_read_rx_descr()
1054 e1000e_read_ext_rx_descr(core, &desc->extended, &buff_addr[0]); in e1000e_read_rx_descr()
1061 e1000e_verify_csum_in_sw(E1000ECore *core, in e1000e_verify_csum_in_sw() argument
1069 if (e1000e_rx_l3_cso_enabled(core)) { in e1000e_verify_csum_in_sw()
1080 if (!e1000e_rx_l4_cso_enabled(core)) { in e1000e_verify_csum_in_sw()
1104 e1000e_is_tcp_ack(E1000ECore *core, struct NetRxPkt *rx_pkt) in e1000e_is_tcp_ack() argument
1110 if (core->mac[RFCTL] & E1000_RFCTL_ACK_DATA_DIS) { in e1000e_is_tcp_ack()
1118 e1000e_build_rx_metadata(E1000ECore *core, in e1000e_build_rx_metadata() argument
1152 if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) { in e1000e_build_rx_metadata()
1164 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && e1000e_is_tcp_ack(core, pkt)) { in e1000e_build_rx_metadata()
1169 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_DIS)) { in e1000e_build_rx_metadata()
1185 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) { in e1000e_build_rx_metadata()
1195 e1000e_verify_csum_in_sw(core, pkt, status_flags, l4hdr_proto); in e1000e_build_rx_metadata()
1199 if (e1000e_rx_l3_cso_enabled(core)) { in e1000e_build_rx_metadata()
1205 if (e1000e_rx_l4_cso_enabled(core)) { in e1000e_build_rx_metadata()
1228 e1000e_write_lgcy_rx_descr(E1000ECore *core, struct e1000_rx_desc *desc, in e1000e_write_lgcy_rx_descr() argument
1241 e1000e_build_rx_metadata(core, pkt, pkt != NULL, in e1000e_write_lgcy_rx_descr()
1251 e1000e_write_ext_rx_descr(E1000ECore *core, union e1000_rx_desc_extended *desc, in e1000e_write_ext_rx_descr() argument
1260 e1000e_build_rx_metadata(core, pkt, pkt != NULL, in e1000e_write_ext_rx_descr()
1270 e1000e_write_ps_rx_descr(E1000ECore *core, in e1000e_write_ps_rx_descr() argument
1287 e1000e_build_rx_metadata(core, pkt, pkt != NULL, in e1000e_write_ps_rx_descr()
1303 e1000e_write_rx_descr(E1000ECore *core, union e1000_rx_desc_union *desc, in e1000e_write_rx_descr() argument
1307 if (e1000e_rx_use_legacy_descriptor(core)) { in e1000e_write_rx_descr()
1309 e1000e_write_lgcy_rx_descr(core, &desc->legacy, pkt, rss_info, in e1000e_write_rx_descr()
1312 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { in e1000e_write_rx_descr()
1313 e1000e_write_ps_rx_descr(core, &desc->packet_split, pkt, rss_info, in e1000e_write_rx_descr()
1317 e1000e_write_ext_rx_descr(core, &desc->extended, pkt, rss_info, in e1000e_write_rx_descr()
1324 e1000e_pci_dma_write_rx_desc(E1000ECore *core, dma_addr_t addr, in e1000e_pci_dma_write_rx_desc() argument
1327 PCIDevice *dev = core->owner; in e1000e_pci_dma_write_rx_desc()
1329 if (e1000e_rx_use_legacy_descriptor(core)) { in e1000e_pci_dma_write_rx_desc()
1342 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { in e1000e_pci_dma_write_rx_desc()
1378 e1000e_write_hdr_frag_to_rx_buffers(E1000ECore *core, in e1000e_write_hdr_frag_to_rx_buffers() argument
1384 assert(data_len <= core->rxbuf_sizes[0] - bastate->written[0]); in e1000e_write_hdr_frag_to_rx_buffers()
1386 pci_dma_write(core->owner, ba[0] + bastate->written[0], data, data_len); in e1000e_write_hdr_frag_to_rx_buffers()
1393 e1000e_write_payload_frag_to_rx_buffers(E1000ECore *core, in e1000e_write_payload_frag_to_rx_buffers() argument
1400 uint32_t cur_buf_len = core->rxbuf_sizes[bastate->cur_idx]; in e1000e_write_payload_frag_to_rx_buffers()
1411 pci_dma_write(core->owner, in e1000e_write_payload_frag_to_rx_buffers()
1428 e1000e_update_rx_stats(E1000ECore *core, size_t pkt_size, size_t pkt_fcs_size) in e1000e_update_rx_stats() argument
1430 eth_pkt_types_e pkt_type = net_rx_pkt_get_packet_type(core->rx_pkt); in e1000e_update_rx_stats()
1431 e1000x_update_rx_total_stats(core->mac, pkt_type, pkt_size, pkt_fcs_size); in e1000e_update_rx_stats()
1435 e1000e_rx_descr_threshold_hit(E1000ECore *core, const E1000ERingInfo *rxi) in e1000e_rx_descr_threshold_hit() argument
1437 return e1000e_ring_free_descr_num(core, rxi) == in e1000e_rx_descr_threshold_hit()
1438 e1000e_ring_len(core, rxi) >> core->rxbuf_min_shift; in e1000e_rx_descr_threshold_hit()
1442 e1000e_do_ps(E1000ECore *core, struct NetRxPkt *pkt, size_t *hdr_len) in e1000e_do_ps() argument
1448 if (!e1000e_rx_use_ps_descriptor(core)) { in e1000e_do_ps()
1462 if (fragment && (core->mac[RFCTL] & E1000_RFCTL_IPFRSP_DIS)) { in e1000e_do_ps()
1473 if ((*hdr_len > core->rxbuf_sizes[0]) || in e1000e_do_ps()
1482 e1000e_write_packet_to_guest(E1000ECore *core, struct NetRxPkt *pkt, in e1000e_write_packet_to_guest() argument
1486 PCIDevice *d = core->owner; in e1000e_write_packet_to_guest()
1495 size_t total_size = size + e1000x_fcs_len(core->mac); in e1000e_write_packet_to_guest()
1498 bool do_ps = e1000e_do_ps(core, pkt, &ps_hdr_len); in e1000e_write_packet_to_guest()
1510 if (desc_size > core->rx_desc_buf_size) { in e1000e_write_packet_to_guest()
1511 desc_size = core->rx_desc_buf_size; in e1000e_write_packet_to_guest()
1514 if (e1000e_ring_empty(core, rxi)) { in e1000e_write_packet_to_guest()
1518 base = e1000e_ring_head_descr(core, rxi); in e1000e_write_packet_to_guest()
1520 pci_dma_read(d, base, &desc, core->rx_desc_len); in e1000e_write_packet_to_guest()
1522 trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len); in e1000e_write_packet_to_guest()
1524 e1000e_read_rx_descr(core, &desc, ba); in e1000e_write_packet_to_guest()
1531 if (copy_size > core->rx_desc_buf_size) { in e1000e_write_packet_to_guest()
1532 copy_size = core->rx_desc_buf_size; in e1000e_write_packet_to_guest()
1543 e1000e_write_hdr_frag_to_rx_buffers(core, ba, in e1000e_write_packet_to_guest()
1562 e1000e_write_hdr_frag_to_rx_buffers(core, ba, &bastate, in e1000e_write_packet_to_guest()
1571 e1000e_write_payload_frag_to_rx_buffers(core, ba, &bastate, in e1000e_write_packet_to_guest()
1586 e1000e_write_payload_frag_to_rx_buffers(core, ba, &bastate, in e1000e_write_packet_to_guest()
1587 (const char *) &fcs_pad, e1000x_fcs_len(core->mac)); in e1000e_write_packet_to_guest()
1598 e1000e_write_rx_descr(core, &desc, is_last ? core->rx_pkt : NULL, in e1000e_write_packet_to_guest()
1600 e1000e_pci_dma_write_rx_desc(core, base, &desc, core->rx_desc_len); in e1000e_write_packet_to_guest()
1602 e1000e_ring_advance(core, rxi, in e1000e_write_packet_to_guest()
1603 core->rx_desc_len / E1000_MIN_RX_DESC_LEN); in e1000e_write_packet_to_guest()
1607 e1000e_update_rx_stats(core, size, total_size); in e1000e_write_packet_to_guest()
1611 e1000e_rx_fix_l4_csum(E1000ECore *core, struct NetRxPkt *pkt) in e1000e_rx_fix_l4_csum() argument
1621 e1000e_receive_iov(E1000ECore *core, const struct iovec *iov, int iovcnt) in e1000e_receive_iov() argument
1623 return e1000e_receive_internal(core, iov, iovcnt, core->has_vnet); in e1000e_receive_iov()
1627 e1000e_receive_internal(E1000ECore *core, const struct iovec *iov, int iovcnt, in e1000e_receive_internal() argument
1643 if (!e1000x_hw_rx_enabled(core->mac)) { in e1000e_receive_internal()
1649 net_rx_pkt_set_vhdr_iovec(core->rx_pkt, iov, iovcnt); in e1000e_receive_internal()
1652 net_rx_pkt_unset_vhdr(core->rx_pkt); in e1000e_receive_internal()
1662 e1000x_inc_reg_if_not_full(core->mac, RUC); in e1000e_receive_internal()
1673 if (e1000x_is_oversized(core->mac, size)) { in e1000e_receive_internal()
1677 net_rx_pkt_set_packet_type(core->rx_pkt, in e1000e_receive_internal()
1680 if (!e1000e_receive_filter(core, buf)) { in e1000e_receive_internal()
1685 net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs, in e1000e_receive_internal()
1686 e1000x_vlan_enabled(core->mac) ? 0 : -1, in e1000e_receive_internal()
1687 core->mac[VET], 0); in e1000e_receive_internal()
1689 e1000e_rss_parse_packet(core, core->rx_pkt, &rss_info); in e1000e_receive_internal()
1690 e1000e_rx_ring_init(core, &rxr, rss_info.queue); in e1000e_receive_internal()
1692 total_size = net_rx_pkt_get_total_len(core->rx_pkt) + in e1000e_receive_internal()
1693 e1000x_fcs_len(core->mac); in e1000e_receive_internal()
1695 if (e1000e_has_rxbufs(core, rxr.i, total_size)) { in e1000e_receive_internal()
1696 e1000e_rx_fix_l4_csum(core, core->rx_pkt); in e1000e_receive_internal()
1698 e1000e_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info); in e1000e_receive_internal()
1703 if (total_size < core->mac[RSRPD]) { in e1000e_receive_internal()
1708 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS) && in e1000e_receive_internal()
1709 (e1000e_is_tcp_ack(core, core->rx_pkt))) { in e1000e_receive_internal()
1714 rdmts_hit = e1000e_rx_descr_threshold_hit(core, rxr.i); in e1000e_receive_internal()
1715 causes |= e1000e_rx_wb_interrupt_cause(core, rxr.i->idx, rdmts_hit); in e1000e_receive_internal()
1725 if (!e1000e_intrmgr_delay_rx_causes(core, &causes)) { in e1000e_receive_internal()
1727 e1000e_set_interrupt_cause(core, causes); in e1000e_receive_internal()
1736 e1000e_have_autoneg(E1000ECore *core) in e1000e_have_autoneg() argument
1738 return core->phy[0][MII_BMCR] & MII_BMCR_AUTOEN; in e1000e_have_autoneg()
1741 static void e1000e_update_flowctl_status(E1000ECore *core) in e1000e_update_flowctl_status() argument
1743 if (e1000e_have_autoneg(core) && in e1000e_update_flowctl_status()
1744 core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP) { in e1000e_update_flowctl_status()
1746 core->mac[CTRL] |= E1000_CTRL_TFCE | E1000_CTRL_RFCE; in e1000e_update_flowctl_status()
1753 e1000e_link_down(E1000ECore *core) in e1000e_link_down() argument
1755 e1000x_update_regs_on_link_down(core->mac, core->phy[0]); in e1000e_link_down()
1756 e1000e_update_flowctl_status(core); in e1000e_link_down()
1760 e1000e_set_phy_ctrl(E1000ECore *core, int index, uint16_t val) in e1000e_set_phy_ctrl() argument
1763 core->phy[0][MII_BMCR] = val & ~(0x3f | in e1000e_set_phy_ctrl()
1768 e1000e_have_autoneg(core)) { in e1000e_set_phy_ctrl()
1769 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); in e1000e_set_phy_ctrl()
1774 e1000e_set_phy_oem_bits(E1000ECore *core, int index, uint16_t val) in e1000e_set_phy_oem_bits() argument
1776 core->phy[0][PHY_OEM_BITS] = val & ~BIT(10); in e1000e_set_phy_oem_bits()
1779 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); in e1000e_set_phy_oem_bits()
1784 e1000e_set_phy_page(E1000ECore *core, int index, uint16_t val) in e1000e_set_phy_page() argument
1786 core->phy[0][PHY_PAGE] = val & PHY_PAGE_RW_MASK; in e1000e_set_phy_page()
1790 e1000e_core_set_link_status(E1000ECore *core) in e1000e_core_set_link_status() argument
1792 NetClientState *nc = qemu_get_queue(core->owner_nic); in e1000e_core_set_link_status()
1793 uint32_t old_status = core->mac[STATUS]; in e1000e_core_set_link_status()
1798 e1000x_update_regs_on_link_down(core->mac, core->phy[0]); in e1000e_core_set_link_status()
1800 if (e1000e_have_autoneg(core) && in e1000e_core_set_link_status()
1801 !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) { in e1000e_core_set_link_status()
1802 e1000x_restart_autoneg(core->mac, core->phy[0], in e1000e_core_set_link_status()
1803 core->autoneg_timer); in e1000e_core_set_link_status()
1805 e1000x_update_regs_on_link_up(core->mac, core->phy[0]); in e1000e_core_set_link_status()
1806 e1000e_start_recv(core); in e1000e_core_set_link_status()
1810 if (core->mac[STATUS] != old_status) { in e1000e_core_set_link_status()
1811 e1000e_set_interrupt_cause(core, E1000_ICR_LSC); in e1000e_core_set_link_status()
1816 e1000e_set_ctrl(E1000ECore *core, int index, uint32_t val) in e1000e_set_ctrl() argument
1821 core->mac[CTRL] = val & ~E1000_CTRL_RST; in e1000e_set_ctrl()
1822 core->mac[CTRL_DUP] = core->mac[CTRL]; in e1000e_set_ctrl()
1834 e1000e_reset(core, true); in e1000e_set_ctrl()
1839 core->mac[STATUS] |= E1000_STATUS_PHYRA; in e1000e_set_ctrl()
1844 e1000e_set_rfctl(E1000ECore *core, int index, uint32_t val) in e1000e_set_rfctl() argument
1860 core->mac[RFCTL] = val; in e1000e_set_rfctl()
1864 e1000e_calc_per_desc_buf_size(E1000ECore *core) in e1000e_calc_per_desc_buf_size() argument
1867 core->rx_desc_buf_size = 0; in e1000e_calc_per_desc_buf_size()
1869 for (i = 0; i < ARRAY_SIZE(core->rxbuf_sizes); i++) { in e1000e_calc_per_desc_buf_size()
1870 core->rx_desc_buf_size += core->rxbuf_sizes[i]; in e1000e_calc_per_desc_buf_size()
1875 e1000e_parse_rxbufsize(E1000ECore *core) in e1000e_parse_rxbufsize() argument
1877 uint32_t rctl = core->mac[RCTL]; in e1000e_parse_rxbufsize()
1879 memset(core->rxbuf_sizes, 0, sizeof(core->rxbuf_sizes)); in e1000e_parse_rxbufsize()
1884 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE0_MASK; in e1000e_parse_rxbufsize()
1885 core->rxbuf_sizes[0] = (bsize >> E1000_PSRCTL_BSIZE0_SHIFT) * 128; in e1000e_parse_rxbufsize()
1887 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE1_MASK; in e1000e_parse_rxbufsize()
1888 core->rxbuf_sizes[1] = (bsize >> E1000_PSRCTL_BSIZE1_SHIFT) * 1024; in e1000e_parse_rxbufsize()
1890 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE2_MASK; in e1000e_parse_rxbufsize()
1891 core->rxbuf_sizes[2] = (bsize >> E1000_PSRCTL_BSIZE2_SHIFT) * 1024; in e1000e_parse_rxbufsize()
1893 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE3_MASK; in e1000e_parse_rxbufsize()
1894 core->rxbuf_sizes[3] = (bsize >> E1000_PSRCTL_BSIZE3_SHIFT) * 1024; in e1000e_parse_rxbufsize()
1897 core->rxbuf_sizes[0] = (flxbuf >> E1000_RCTL_FLXBUF_SHIFT) * 1024; in e1000e_parse_rxbufsize()
1899 core->rxbuf_sizes[0] = e1000x_rxbufsize(rctl); in e1000e_parse_rxbufsize()
1902 trace_e1000e_rx_desc_buff_sizes(core->rxbuf_sizes[0], core->rxbuf_sizes[1], in e1000e_parse_rxbufsize()
1903 core->rxbuf_sizes[2], core->rxbuf_sizes[3]); in e1000e_parse_rxbufsize()
1905 e1000e_calc_per_desc_buf_size(core); in e1000e_parse_rxbufsize()
1909 e1000e_calc_rxdesclen(E1000ECore *core) in e1000e_calc_rxdesclen() argument
1911 if (e1000e_rx_use_legacy_descriptor(core)) { in e1000e_calc_rxdesclen()
1912 core->rx_desc_len = sizeof(struct e1000_rx_desc); in e1000e_calc_rxdesclen()
1914 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { in e1000e_calc_rxdesclen()
1915 core->rx_desc_len = sizeof(union e1000_rx_desc_packet_split); in e1000e_calc_rxdesclen()
1917 core->rx_desc_len = sizeof(union e1000_rx_desc_extended); in e1000e_calc_rxdesclen()
1920 trace_e1000e_rx_desc_len(core->rx_desc_len); in e1000e_calc_rxdesclen()
1924 e1000e_set_rx_control(E1000ECore *core, int index, uint32_t val) in e1000e_set_rx_control() argument
1926 core->mac[RCTL] = val; in e1000e_set_rx_control()
1927 trace_e1000e_rx_set_rctl(core->mac[RCTL]); in e1000e_set_rx_control()
1930 e1000e_parse_rxbufsize(core); in e1000e_set_rx_control()
1931 e1000e_calc_rxdesclen(core); in e1000e_set_rx_control()
1932 core->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1 + in e1000e_set_rx_control()
1935 e1000e_start_recv(core); in e1000e_set_rx_control()
1958 if (timer->core->mac[timer->delay_reg] != 0) { in e1000e_postpone_interrupt()
1966 e1000e_itr_should_postpone(E1000ECore *core) in e1000e_itr_should_postpone() argument
1968 return e1000e_postpone_interrupt(&core->itr); in e1000e_itr_should_postpone()
1972 e1000e_eitr_should_postpone(E1000ECore *core, int idx) in e1000e_eitr_should_postpone() argument
1974 return e1000e_postpone_interrupt(&core->eitr[idx]); in e1000e_eitr_should_postpone()
1978 e1000e_msix_notify_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg) in e1000e_msix_notify_one() argument
1985 if (!e1000e_eitr_should_postpone(core, vec)) { in e1000e_msix_notify_one()
1987 msix_notify(core->owner, vec); in e1000e_msix_notify_one()
1996 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_EIAME) { in e1000e_msix_notify_one()
1997 trace_e1000e_irq_iam_clear_eiame(core->mac[IAM], cause); in e1000e_msix_notify_one()
1998 core->mac[IAM] &= ~cause; in e1000e_msix_notify_one()
2001 trace_e1000e_irq_icr_clear_eiac(core->mac[ICR], core->mac[EIAC]); in e1000e_msix_notify_one()
2003 effective_eiac = core->mac[EIAC] & cause; in e1000e_msix_notify_one()
2005 core->mac[ICR] &= ~effective_eiac; in e1000e_msix_notify_one()
2007 if (!(core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { in e1000e_msix_notify_one()
2008 core->mac[IMS] &= ~effective_eiac; in e1000e_msix_notify_one()
2013 e1000e_msix_notify(E1000ECore *core, uint32_t causes) in e1000e_msix_notify() argument
2016 e1000e_msix_notify_one(core, E1000_ICR_RXQ0, in e1000e_msix_notify()
2017 E1000_IVAR_RXQ0(core->mac[IVAR])); in e1000e_msix_notify()
2021 e1000e_msix_notify_one(core, E1000_ICR_RXQ1, in e1000e_msix_notify()
2022 E1000_IVAR_RXQ1(core->mac[IVAR])); in e1000e_msix_notify()
2026 e1000e_msix_notify_one(core, E1000_ICR_TXQ0, in e1000e_msix_notify()
2027 E1000_IVAR_TXQ0(core->mac[IVAR])); in e1000e_msix_notify()
2031 e1000e_msix_notify_one(core, E1000_ICR_TXQ1, in e1000e_msix_notify()
2032 E1000_IVAR_TXQ1(core->mac[IVAR])); in e1000e_msix_notify()
2036 e1000e_msix_notify_one(core, E1000_ICR_OTHER, in e1000e_msix_notify()
2037 E1000_IVAR_OTHER(core->mac[IVAR])); in e1000e_msix_notify()
2042 e1000e_msix_clear_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg) in e1000e_msix_clear_one() argument
2048 msix_clr_pending(core->owner, vec); in e1000e_msix_clear_one()
2058 e1000e_msix_clear(E1000ECore *core, uint32_t causes) in e1000e_msix_clear() argument
2061 e1000e_msix_clear_one(core, E1000_ICR_RXQ0, in e1000e_msix_clear()
2062 E1000_IVAR_RXQ0(core->mac[IVAR])); in e1000e_msix_clear()
2066 e1000e_msix_clear_one(core, E1000_ICR_RXQ1, in e1000e_msix_clear()
2067 E1000_IVAR_RXQ1(core->mac[IVAR])); in e1000e_msix_clear()
2071 e1000e_msix_clear_one(core, E1000_ICR_TXQ0, in e1000e_msix_clear()
2072 E1000_IVAR_TXQ0(core->mac[IVAR])); in e1000e_msix_clear()
2076 e1000e_msix_clear_one(core, E1000_ICR_TXQ1, in e1000e_msix_clear()
2077 E1000_IVAR_TXQ1(core->mac[IVAR])); in e1000e_msix_clear()
2081 e1000e_msix_clear_one(core, E1000_ICR_OTHER, in e1000e_msix_clear()
2082 E1000_IVAR_OTHER(core->mac[IVAR])); in e1000e_msix_clear()
2087 e1000e_fix_icr_asserted(E1000ECore *core) in e1000e_fix_icr_asserted() argument
2089 core->mac[ICR] &= ~E1000_ICR_ASSERTED; in e1000e_fix_icr_asserted()
2090 if (core->mac[ICR]) { in e1000e_fix_icr_asserted()
2091 core->mac[ICR] |= E1000_ICR_ASSERTED; in e1000e_fix_icr_asserted()
2094 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]); in e1000e_fix_icr_asserted()
2097 static void e1000e_raise_interrupts(E1000ECore *core, in e1000e_raise_interrupts() argument
2100 bool is_msix = msix_enabled(core->owner); in e1000e_raise_interrupts()
2101 uint32_t old_causes = core->mac[IMS] & core->mac[ICR]; in e1000e_raise_interrupts()
2105 core->mac[index], core->mac[index] | causes); in e1000e_raise_interrupts()
2107 core->mac[index] |= causes; in e1000e_raise_interrupts()
2111 if (core->mac[ICR] & E1000_ICR_OTHER_CAUSES) { in e1000e_raise_interrupts()
2112 core->mac[ICR] |= E1000_ICR_OTHER; in e1000e_raise_interrupts()
2113 trace_e1000e_irq_add_msi_other(core->mac[ICR]); in e1000e_raise_interrupts()
2117 e1000e_fix_icr_asserted(core); in e1000e_raise_interrupts()
2127 core->mac[ICS] = core->mac[ICR]; in e1000e_raise_interrupts()
2129 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS], in e1000e_raise_interrupts()
2130 core->mac[ICR], core->mac[IMS]); in e1000e_raise_interrupts()
2132 raised_causes = core->mac[IMS] & core->mac[ICR] & ~old_causes; in e1000e_raise_interrupts()
2138 e1000e_msix_notify(core, raised_causes & ~E1000_ICR_ASSERTED); in e1000e_raise_interrupts()
2139 } else if (!e1000e_itr_should_postpone(core)) { in e1000e_raise_interrupts()
2140 if (msi_enabled(core->owner)) { in e1000e_raise_interrupts()
2142 msi_notify(core->owner, 0); in e1000e_raise_interrupts()
2144 e1000e_raise_legacy_irq(core); in e1000e_raise_interrupts()
2149 static void e1000e_lower_interrupts(E1000ECore *core, in e1000e_lower_interrupts() argument
2153 core->mac[index], core->mac[index] & ~causes); in e1000e_lower_interrupts()
2155 core->mac[index] &= ~causes; in e1000e_lower_interrupts()
2165 core->mac[ICS] = core->mac[ICR]; in e1000e_lower_interrupts()
2167 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS], in e1000e_lower_interrupts()
2168 core->mac[ICR], core->mac[IMS]); in e1000e_lower_interrupts()
2170 if (!(core->mac[IMS] & core->mac[ICR]) && in e1000e_lower_interrupts()
2171 !msix_enabled(core->owner) && !msi_enabled(core->owner)) { in e1000e_lower_interrupts()
2172 e1000e_lower_legacy_irq(core); in e1000e_lower_interrupts()
2177 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val) in e1000e_set_interrupt_cause() argument
2179 val |= e1000e_intmgr_collect_delayed_causes(core); in e1000e_set_interrupt_cause()
2180 e1000e_raise_interrupts(core, ICR, val); in e1000e_set_interrupt_cause()
2186 E1000ECore *core = opaque; in e1000e_autoneg_timer() local
2187 if (!qemu_get_queue(core->owner_nic)->link_down) { in e1000e_autoneg_timer()
2188 e1000x_update_regs_on_autoneg_done(core->mac, core->phy[0]); in e1000e_autoneg_timer()
2189 e1000e_start_recv(core); in e1000e_autoneg_timer()
2191 e1000e_update_flowctl_status(core); in e1000e_autoneg_timer()
2193 e1000e_set_interrupt_cause(core, E1000_ICR_LSC); in e1000e_autoneg_timer()
2253 e1000e_phy_reg_check_cap(E1000ECore *core, uint32_t addr, in e1000e_phy_reg_check_cap() argument
2258 : core->phy[0][PHY_PAGE]; in e1000e_phy_reg_check_cap()
2268 e1000e_phy_reg_write(E1000ECore *core, uint8_t page, in e1000e_phy_reg_write() argument
2275 e1000e_phyreg_writeops[page][addr](core, addr, data); in e1000e_phy_reg_write()
2277 core->phy[page][addr] = data; in e1000e_phy_reg_write()
2282 e1000e_set_mdic(E1000ECore *core, int index, uint32_t val) in e1000e_set_mdic() argument
2289 val = core->mac[MDIC] | E1000_MDIC_ERROR; in e1000e_set_mdic()
2291 if (!e1000e_phy_reg_check_cap(core, addr, PHY_R, &page)) { in e1000e_set_mdic()
2295 val = (val ^ data) | core->phy[page][addr]; in e1000e_set_mdic()
2299 if (!e1000e_phy_reg_check_cap(core, addr, PHY_W, &page)) { in e1000e_set_mdic()
2304 e1000e_phy_reg_write(core, page, addr, data); in e1000e_set_mdic()
2307 core->mac[MDIC] = val | E1000_MDIC_READY; in e1000e_set_mdic()
2310 e1000e_set_interrupt_cause(core, E1000_ICR_MDAC); in e1000e_set_mdic()
2315 e1000e_set_rdt(E1000ECore *core, int index, uint32_t val) in e1000e_set_rdt() argument
2317 core->mac[index] = val & 0xffff; in e1000e_set_rdt()
2319 e1000e_start_recv(core); in e1000e_set_rdt()
2323 e1000e_set_status(E1000ECore *core, int index, uint32_t val) in e1000e_set_status() argument
2326 core->mac[index] &= ~E1000_STATUS_PHYRA; in e1000e_set_status()
2331 e1000e_set_ctrlext(E1000ECore *core, int index, uint32_t val) in e1000e_set_ctrlext() argument
2338 core->mac[CTRL_EXT] = val; in e1000e_set_ctrlext()
2342 e1000e_set_pbaclr(E1000ECore *core, int index, uint32_t val) in e1000e_set_pbaclr() argument
2346 core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK; in e1000e_set_pbaclr()
2348 if (!msix_enabled(core->owner)) { in e1000e_set_pbaclr()
2353 if (core->mac[PBACLR] & BIT(i)) { in e1000e_set_pbaclr()
2354 msix_clr_pending(core->owner, i); in e1000e_set_pbaclr()
2360 e1000e_set_fcrth(E1000ECore *core, int index, uint32_t val) in e1000e_set_fcrth() argument
2362 core->mac[FCRTH] = val & 0xFFF8; in e1000e_set_fcrth()
2366 e1000e_set_fcrtl(E1000ECore *core, int index, uint32_t val) in e1000e_set_fcrtl() argument
2368 core->mac[FCRTL] = val & 0x8000FFF8; in e1000e_set_fcrtl()
2373 e1000e_set_##num##bit(E1000ECore *core, int index, uint32_t val) \
2375 core->mac[index] = val & (BIT(num) - 1); \
2386 e1000e_set_vet(E1000ECore *core, int index, uint32_t val) in e1000e_set_vet() argument
2388 core->mac[VET] = val & 0xffff; in e1000e_set_vet()
2389 trace_e1000e_vlan_vet(core->mac[VET]); in e1000e_set_vet()
2393 e1000e_set_dlen(E1000ECore *core, int index, uint32_t val) in e1000e_set_dlen() argument
2395 core->mac[index] = val & E1000_XDLEN_MASK; in e1000e_set_dlen()
2399 e1000e_set_dbal(E1000ECore *core, int index, uint32_t val) in e1000e_set_dbal() argument
2401 core->mac[index] = val & E1000_XDBAL_MASK; in e1000e_set_dbal()
2405 e1000e_set_tctl(E1000ECore *core, int index, uint32_t val) in e1000e_set_tctl() argument
2408 core->mac[index] = val; in e1000e_set_tctl()
2410 if (core->mac[TARC0] & E1000_TARC_ENABLE) { in e1000e_set_tctl()
2411 e1000e_tx_ring_init(core, &txr, 0); in e1000e_set_tctl()
2412 e1000e_start_xmit(core, &txr); in e1000e_set_tctl()
2415 if (core->mac[TARC1] & E1000_TARC_ENABLE) { in e1000e_set_tctl()
2416 e1000e_tx_ring_init(core, &txr, 1); in e1000e_set_tctl()
2417 e1000e_start_xmit(core, &txr); in e1000e_set_tctl()
2422 e1000e_set_tdt(E1000ECore *core, int index, uint32_t val) in e1000e_set_tdt() argument
2428 core->mac[index] = val & 0xffff; in e1000e_set_tdt()
2430 if (core->mac[tarc_reg] & E1000_TARC_ENABLE) { in e1000e_set_tdt()
2431 e1000e_tx_ring_init(core, &txr, qidx); in e1000e_set_tdt()
2432 e1000e_start_xmit(core, &txr); in e1000e_set_tdt()
2437 e1000e_set_ics(E1000ECore *core, int index, uint32_t val) in e1000e_set_ics() argument
2440 e1000e_set_interrupt_cause(core, val); in e1000e_set_ics()
2444 e1000e_set_icr(E1000ECore *core, int index, uint32_t val) in e1000e_set_icr() argument
2446 if ((core->mac[ICR] & E1000_ICR_ASSERTED) && in e1000e_set_icr()
2447 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { in e1000e_set_icr()
2449 e1000e_lower_interrupts(core, IMS, core->mac[IAM]); in e1000e_set_icr()
2459 e1000e_lower_interrupts(core, ICR, val); in e1000e_set_icr()
2463 e1000e_set_imc(E1000ECore *core, int index, uint32_t val) in e1000e_set_imc() argument
2466 e1000e_lower_interrupts(core, IMS, val); in e1000e_set_imc()
2470 e1000e_set_ims(E1000ECore *core, int index, uint32_t val) in e1000e_set_ims() argument
2488 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PBA_CLR) && in e1000e_set_ims()
2489 msix_enabled(core->owner)) { in e1000e_set_ims()
2490 e1000e_msix_clear(core, valid_val); in e1000e_set_ims()
2494 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_INT_TIMERS_CLEAR_ENA)) { in e1000e_set_ims()
2496 e1000e_intrmgr_fire_all_timers(core); in e1000e_set_ims()
2499 e1000e_raise_interrupts(core, IMS, valid_val); in e1000e_set_ims()
2503 e1000e_set_rdtr(E1000ECore *core, int index, uint32_t val) in e1000e_set_rdtr() argument
2505 e1000e_set_16bit(core, index, val); in e1000e_set_rdtr()
2507 if ((val & E1000_RDTR_FPD) && (core->rdtr.running)) { in e1000e_set_rdtr()
2509 e1000e_intrmgr_fire_delayed_interrupts(core); in e1000e_set_rdtr()
2516 e1000e_set_tidv(E1000ECore *core, int index, uint32_t val) in e1000e_set_tidv() argument
2518 e1000e_set_16bit(core, index, val); in e1000e_set_tidv()
2520 if ((val & E1000_TIDV_FPD) && (core->tidv.running)) { in e1000e_set_tidv()
2522 e1000e_intrmgr_fire_delayed_interrupts(core); in e1000e_set_tidv()
2529 e1000e_mac_readreg(E1000ECore *core, int index) in e1000e_mac_readreg() argument
2531 return core->mac[index]; in e1000e_mac_readreg()
2535 e1000e_mac_ics_read(E1000ECore *core, int index) in e1000e_mac_ics_read() argument
2537 trace_e1000e_irq_read_ics(core->mac[ICS]); in e1000e_mac_ics_read()
2538 return core->mac[ICS]; in e1000e_mac_ics_read()
2542 e1000e_mac_ims_read(E1000ECore *core, int index) in e1000e_mac_ims_read() argument
2544 trace_e1000e_irq_read_ims(core->mac[IMS]); in e1000e_mac_ims_read()
2545 return core->mac[IMS]; in e1000e_mac_ims_read()
2549 e1000e_mac_swsm_read(E1000ECore *core, int index) in e1000e_mac_swsm_read() argument
2551 uint32_t val = core->mac[SWSM]; in e1000e_mac_swsm_read()
2552 core->mac[SWSM] = val | E1000_SWSM_SMBI; in e1000e_mac_swsm_read()
2557 e1000e_mac_itr_read(E1000ECore *core, int index) in e1000e_mac_itr_read() argument
2559 return core->itr_guest_value; in e1000e_mac_itr_read()
2563 e1000e_mac_eitr_read(E1000ECore *core, int index) in e1000e_mac_eitr_read() argument
2565 return core->eitr_guest_value[index - EITR]; in e1000e_mac_eitr_read()
2569 e1000e_mac_icr_read(E1000ECore *core, int index) in e1000e_mac_icr_read() argument
2571 uint32_t ret = core->mac[ICR]; in e1000e_mac_icr_read()
2573 if (core->mac[IMS] == 0) { in e1000e_mac_icr_read()
2575 e1000e_lower_interrupts(core, ICR, 0xffffffff); in e1000e_mac_icr_read()
2578 if (!msix_enabled(core->owner)) { in e1000e_mac_icr_read()
2580 e1000e_lower_interrupts(core, ICR, 0xffffffff); in e1000e_mac_icr_read()
2583 if (core->mac[ICR] & E1000_ICR_ASSERTED) { in e1000e_mac_icr_read()
2584 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME) { in e1000e_mac_icr_read()
2586 e1000e_lower_interrupts(core, ICR, 0xffffffff); in e1000e_mac_icr_read()
2588 e1000e_lower_interrupts(core, IMS, core->mac[IAM]); in e1000e_mac_icr_read()
2610 if (core->mac[ICR] & core->mac[IMS]) { in e1000e_mac_icr_read()
2611 trace_e1000e_irq_icr_clear_icr_bit_ims(core->mac[ICR], in e1000e_mac_icr_read()
2612 core->mac[IMS]); in e1000e_mac_icr_read()
2613 e1000e_lower_interrupts(core, ICR, 0xffffffff); in e1000e_mac_icr_read()
2621 e1000e_mac_read_clr4(E1000ECore *core, int index) in e1000e_mac_read_clr4() argument
2623 uint32_t ret = core->mac[index]; in e1000e_mac_read_clr4()
2625 core->mac[index] = 0; in e1000e_mac_read_clr4()
2630 e1000e_mac_read_clr8(E1000ECore *core, int index) in e1000e_mac_read_clr8() argument
2632 uint32_t ret = core->mac[index]; in e1000e_mac_read_clr8()
2634 core->mac[index] = 0; in e1000e_mac_read_clr8()
2635 core->mac[index - 1] = 0; in e1000e_mac_read_clr8()
2640 e1000e_get_ctrl(E1000ECore *core, int index) in e1000e_get_ctrl() argument
2642 uint32_t val = core->mac[CTRL]; in e1000e_get_ctrl()
2656 e1000e_get_status(E1000ECore *core, int index) in e1000e_get_status() argument
2658 uint32_t res = core->mac[STATUS]; in e1000e_get_status()
2660 if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE)) { in e1000e_get_status()
2664 if (core->mac[CTRL] & E1000_CTRL_FRCDPX) { in e1000e_get_status()
2665 res |= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0; in e1000e_get_status()
2670 if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) || in e1000e_get_status()
2671 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) { in e1000e_get_status()
2672 switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) { in e1000e_get_status()
2698 e1000e_get_tarc(E1000ECore *core, int index) in e1000e_get_tarc() argument
2700 return core->mac[index] & ((BIT(11) - 1) | in e1000e_get_tarc()
2708 e1000e_mac_writereg(E1000ECore *core, int index, uint32_t val) in e1000e_mac_writereg() argument
2710 core->mac[index] = val; in e1000e_mac_writereg()
2714 e1000e_mac_setmacaddr(E1000ECore *core, int index, uint32_t val) in e1000e_mac_setmacaddr() argument
2718 core->mac[index] = val; in e1000e_mac_setmacaddr()
2720 macaddr[0] = cpu_to_le32(core->mac[RA]); in e1000e_mac_setmacaddr()
2721 macaddr[1] = cpu_to_le32(core->mac[RA + 1]); in e1000e_mac_setmacaddr()
2722 qemu_format_nic_info_str(qemu_get_queue(core->owner_nic), in e1000e_mac_setmacaddr()
2729 e1000e_set_eecd(E1000ECore *core, int index, uint32_t val) in e1000e_set_eecd() argument
2735 core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits); in e1000e_set_eecd()
2739 e1000e_set_eerd(E1000ECore *core, int index, uint32_t val) in e1000e_set_eerd() argument
2746 data = core->eeprom[addr]; in e1000e_set_eerd()
2750 core->mac[EERD] = flags | in e1000e_set_eerd()
2756 e1000e_set_eewr(E1000ECore *core, int index, uint32_t val) in e1000e_set_eewr() argument
2763 core->eeprom[addr] = data; in e1000e_set_eewr()
2767 core->mac[EERD] = flags | in e1000e_set_eewr()
2773 e1000e_set_rxdctl(E1000ECore *core, int index, uint32_t val) in e1000e_set_rxdctl() argument
2775 core->mac[RXDCTL] = core->mac[RXDCTL1] = val; in e1000e_set_rxdctl()
2779 e1000e_set_itr(E1000ECore *core, int index, uint32_t val) in e1000e_set_itr() argument
2785 core->itr_guest_value = interval; in e1000e_set_itr()
2786 core->mac[index] = MAX(interval, E1000E_MIN_XITR); in e1000e_set_itr()
2790 e1000e_set_eitr(E1000ECore *core, int index, uint32_t val) in e1000e_set_eitr() argument
2797 core->eitr_guest_value[eitr_num] = interval; in e1000e_set_eitr()
2798 core->mac[index] = MAX(interval, E1000E_MIN_XITR); in e1000e_set_eitr()
2802 e1000e_set_psrctl(E1000ECore *core, int index, uint32_t val) in e1000e_set_psrctl() argument
2804 if (core->mac[RCTL] & E1000_RCTL_DTYP_MASK) { in e1000e_set_psrctl()
2819 core->mac[PSRCTL] = val; in e1000e_set_psrctl()
2823 e1000e_update_rx_offloads(E1000ECore *core) in e1000e_update_rx_offloads() argument
2825 int cso_state = e1000e_rx_l4_cso_enabled(core); in e1000e_update_rx_offloads()
2829 if (core->has_vnet) { in e1000e_update_rx_offloads()
2830 qemu_set_offload(qemu_get_queue(core->owner_nic)->peer, in e1000e_update_rx_offloads()
2836 e1000e_set_rxcsum(E1000ECore *core, int index, uint32_t val) in e1000e_set_rxcsum() argument
2838 core->mac[RXCSUM] = val; in e1000e_set_rxcsum()
2839 e1000e_update_rx_offloads(core); in e1000e_set_rxcsum()
2843 e1000e_set_gcr(E1000ECore *core, int index, uint32_t val) in e1000e_set_gcr() argument
2845 uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS; in e1000e_set_gcr()
2846 core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits; in e1000e_set_gcr()
2849 static uint32_t e1000e_get_systiml(E1000ECore *core, int index) in e1000e_get_systiml() argument
2851 e1000x_timestamp(core->mac, core->timadj, SYSTIML, SYSTIMH); in e1000e_get_systiml()
2852 return core->mac[SYSTIML]; in e1000e_get_systiml()
2855 static uint32_t e1000e_get_rxsatrh(E1000ECore *core, int index) in e1000e_get_rxsatrh() argument
2857 core->mac[TSYNCRXCTL] &= ~E1000_TSYNCRXCTL_VALID; in e1000e_get_rxsatrh()
2858 return core->mac[RXSATRH]; in e1000e_get_rxsatrh()
2861 static uint32_t e1000e_get_txstmph(E1000ECore *core, int index) in e1000e_get_txstmph() argument
2863 core->mac[TSYNCTXCTL] &= ~E1000_TSYNCTXCTL_VALID; in e1000e_get_txstmph()
2864 return core->mac[TXSTMPH]; in e1000e_get_txstmph()
2867 static void e1000e_set_timinca(E1000ECore *core, int index, uint32_t val) in e1000e_set_timinca() argument
2869 e1000x_set_timinca(core->mac, &core->timadj, val); in e1000e_set_timinca()
2872 static void e1000e_set_timadjh(E1000ECore *core, int index, uint32_t val) in e1000e_set_timadjh() argument
2874 core->mac[TIMADJH] = val; in e1000e_set_timadjh()
2875 core->timadj += core->mac[TIMADJL] | ((int64_t)core->mac[TIMADJH] << 32); in e1000e_set_timadjh()
3273 e1000e_core_write(E1000ECore *core, hwaddr addr, uint64_t val, unsigned size) in e1000e_core_write() argument
3282 e1000e_macreg_writeops[index](core, index, val); in e1000e_core_write()
3291 e1000e_core_read(E1000ECore *core, hwaddr addr, unsigned size) in e1000e_core_read() argument
3300 val = e1000e_macreg_readops[index](core, index); in e1000e_core_read()
3310 e1000e_autoneg_resume(E1000ECore *core) in e1000e_autoneg_resume() argument
3312 if (e1000e_have_autoneg(core) && in e1000e_autoneg_resume()
3313 !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) { in e1000e_autoneg_resume()
3314 qemu_get_queue(core->owner_nic)->link_down = false; in e1000e_autoneg_resume()
3315 timer_mod(core->autoneg_timer, in e1000e_autoneg_resume()
3321 e1000e_core_pci_realize(E1000ECore *core, in e1000e_core_pci_realize() argument
3328 core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, in e1000e_core_pci_realize()
3329 e1000e_autoneg_timer, core); in e1000e_core_pci_realize()
3330 e1000e_intrmgr_pci_realize(core); in e1000e_core_pci_realize()
3333 net_tx_pkt_init(&core->tx[i].tx_pkt, E1000E_MAX_TX_FRAGS); in e1000e_core_pci_realize()
3336 net_rx_pkt_init(&core->rx_pkt); in e1000e_core_pci_realize()
3338 e1000x_core_prepare_eeprom(core->eeprom, in e1000e_core_pci_realize()
3341 PCI_DEVICE_GET_CLASS(core->owner)->device_id, in e1000e_core_pci_realize()
3343 e1000e_update_rx_offloads(core); in e1000e_core_pci_realize()
3347 e1000e_core_pci_uninit(E1000ECore *core) in e1000e_core_pci_uninit() argument
3351 timer_free(core->autoneg_timer); in e1000e_core_pci_uninit()
3353 e1000e_intrmgr_pci_unint(core); in e1000e_core_pci_uninit()
3356 net_tx_pkt_uninit(core->tx[i].tx_pkt); in e1000e_core_pci_uninit()
3359 net_rx_pkt_uninit(core->rx_pkt); in e1000e_core_pci_uninit()
3451 static void e1000e_reset(E1000ECore *core, bool sw) in e1000e_reset() argument
3455 timer_del(core->autoneg_timer); in e1000e_reset()
3457 e1000e_intrmgr_reset(core); in e1000e_reset()
3459 memset(core->phy, 0, sizeof core->phy); in e1000e_reset()
3460 memcpy(core->phy, e1000e_phy_reg_init, sizeof e1000e_phy_reg_init); in e1000e_reset()
3467 core->mac[i] = i < ARRAY_SIZE(e1000e_mac_reg_init) ? in e1000e_reset()
3471 core->rxbuf_min_shift = 1 + E1000_RING_DESC_LEN_SHIFT; in e1000e_reset()
3473 if (qemu_get_queue(core->owner_nic)->link_down) { in e1000e_reset()
3474 e1000e_link_down(core); in e1000e_reset()
3477 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac); in e1000e_reset()
3479 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { in e1000e_reset()
3480 memset(&core->tx[i].props, 0, sizeof(core->tx[i].props)); in e1000e_reset()
3481 core->tx[i].skip_cp = false; in e1000e_reset()
3486 e1000e_core_reset(E1000ECore *core) in e1000e_core_reset() argument
3488 e1000e_reset(core, false); in e1000e_core_reset()
3491 void e1000e_core_pre_save(E1000ECore *core) in e1000e_core_pre_save() argument
3494 NetClientState *nc = qemu_get_queue(core->owner_nic); in e1000e_core_pre_save()
3501 if (nc->link_down && e1000e_have_autoneg(core)) { in e1000e_core_pre_save()
3502 core->phy[0][MII_BMSR] |= MII_BMSR_AN_COMP; in e1000e_core_pre_save()
3503 e1000e_update_flowctl_status(core); in e1000e_core_pre_save()
3506 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { in e1000e_core_pre_save()
3507 if (net_tx_pkt_has_fragments(core->tx[i].tx_pkt)) { in e1000e_core_pre_save()
3508 core->tx[i].skip_cp = true; in e1000e_core_pre_save()
3514 e1000e_core_post_load(E1000ECore *core) in e1000e_core_post_load() argument
3516 NetClientState *nc = qemu_get_queue(core->owner_nic); in e1000e_core_post_load()
3520 * to link status bit in core.mac[STATUS]. in e1000e_core_post_load()
3522 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0; in e1000e_core_post_load()
3528 e1000e_intrmgr_resume(core); in e1000e_core_post_load()
3529 e1000e_autoneg_resume(core); in e1000e_core_post_load()