Lines Matching full:mac
94 e1000x_inc_reg_if_not_full(core->mac, IAC); in e1000e_raise_legacy_irq()
108 int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] * in e1000e_intrmgr_rearm_timer()
160 if (timer->core->mac[IMS] & timer->core->mac[ICR]) { in e1000e_intrmgr_on_throttling_timer()
258 uint32_t rdtr = core->mac[RDTR]; in e1000e_intrmgr_delay_rx_causes()
259 uint32_t radv = core->mac[RADV]; in e1000e_intrmgr_delay_rx_causes()
260 uint32_t raid = core->mac[RAID]; in e1000e_intrmgr_delay_rx_causes()
270 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS)) { in e1000e_intrmgr_delay_rx_causes()
332 if (!core->tadv.running && (core->mac[TADV] != 0)) { in e1000e_intrmgr_delay_tx_causes()
437 return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true; in e1000e_rx_csum_enabled()
443 return (core->mac[RFCTL] & E1000_RFCTL_EXTEN) ? false : true; in e1000e_rx_use_legacy_descriptor()
450 (core->mac[RCTL] & E1000_RCTL_DTYP_PS); in e1000e_rx_use_ps_descriptor()
456 return E1000_MRQC_ENABLED(core->mac[MRQC]) && in e1000e_rss_enabled()
479 trace_e1000e_rx_rss_ip4(l4hdr_proto, core->mac[MRQC], in e1000e_rss_get_hash_type()
480 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]), in e1000e_rss_get_hash_type()
481 E1000_MRQC_EN_IPV4(core->mac[MRQC])); in e1000e_rss_get_hash_type()
484 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) { in e1000e_rss_get_hash_type()
488 if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) { in e1000e_rss_get_hash_type()
494 bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS; in e1000e_rss_get_hash_type()
495 bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS; in e1000e_rss_get_hash_type()
504 trace_e1000e_rx_rss_ip6_rfctl(core->mac[RFCTL]); in e1000e_rss_get_hash_type()
509 core->mac[MRQC], in e1000e_rss_get_hash_type()
510 E1000_MRQC_EN_TCPIPV6EX(core->mac[MRQC]), in e1000e_rss_get_hash_type()
511 E1000_MRQC_EN_IPV6EX(core->mac[MRQC]), in e1000e_rss_get_hash_type()
512 E1000_MRQC_EN_IPV6(core->mac[MRQC])); in e1000e_rss_get_hash_type()
519 E1000_MRQC_EN_TCPIPV6EX(core->mac[MRQC])) { in e1000e_rss_get_hash_type()
523 if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) { in e1000e_rss_get_hash_type()
529 if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) { in e1000e_rss_get_hash_type()
567 return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]); in e1000e_rss_calc_hash()
599 info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash); in e1000e_rss_parse_packet()
611 e1000x_inc_reg_if_not_full(core->mac, TSCTC); in e1000e_setup_tx_offloads()
650 ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) { in e1000e_tx_pkt_send()
666 e1000x_increase_size_stats(core->mac, PTCregs, tot_len); in e1000e_on_tx_done_update_stats()
667 e1000x_inc_reg_if_not_full(core->mac, TPT); in e1000e_on_tx_done_update_stats()
668 e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len); in e1000e_on_tx_done_update_stats()
672 e1000x_inc_reg_if_not_full(core->mac, BPTC); in e1000e_on_tx_done_update_stats()
675 e1000x_inc_reg_if_not_full(core->mac, MPTC); in e1000e_on_tx_done_update_stats()
683 e1000x_inc_reg_if_not_full(core->mac, GPTC); in e1000e_on_tx_done_update_stats()
684 e1000x_grow_8reg_if_not_full(core->mac, GOTCL, tot_len); in e1000e_on_tx_done_update_stats()
726 if (e1000x_vlan_enabled(core->mac) && in e1000e_process_tx_desc()
729 le16_to_cpu(dp->upper.fields.special), core->mac[VET]); in e1000e_process_tx_desc()
772 !(core->mac[IVAR] & E1000_IVAR_TX_INT_EVERY_WB)) { in e1000e_txdesc_writeback()
798 return core->mac[r->dh] == core->mac[r->dt] || in e1000e_ring_empty()
799 core->mac[r->dt] >= core->mac[r->dlen] / E1000_RING_DESC_LEN; in e1000e_ring_empty()
805 uint64_t bah = core->mac[r->dbah]; in e1000e_ring_base()
806 uint64_t bal = core->mac[r->dbal]; in e1000e_ring_base()
814 return e1000e_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh]; in e1000e_ring_head_descr()
820 core->mac[r->dh] += count; in e1000e_ring_advance()
822 if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) { in e1000e_ring_advance()
823 core->mac[r->dh] = 0; in e1000e_ring_advance()
830 trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen], in e1000e_ring_free_descr_num()
831 core->mac[r->dh], core->mac[r->dt]); in e1000e_ring_free_descr_num()
833 if (core->mac[r->dh] <= core->mac[r->dt]) { in e1000e_ring_free_descr_num()
834 return core->mac[r->dt] - core->mac[r->dh]; in e1000e_ring_free_descr_num()
837 if (core->mac[r->dh] > core->mac[r->dt]) { in e1000e_ring_free_descr_num()
838 return core->mac[r->dlen] / E1000_RING_DESC_LEN + in e1000e_ring_free_descr_num()
839 core->mac[r->dt] - core->mac[r->dh]; in e1000e_ring_free_descr_num()
848 return core->mac[r->dlen] > 0; in e1000e_ring_enabled()
854 return core->mac[r->dlen]; in e1000e_ring_len()
908 if (!(core->mac[TCTL] & E1000_TCTL_EN)) { in e1000e_start_xmit()
964 if (!e1000x_rx_ready(core->owner, core->mac)) { in e1000e_can_receive()
997 return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD); in e1000e_rx_l3_cso_enabled()
1003 return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD); in e1000e_rx_l4_cso_enabled()
1009 return (!e1000x_is_vlan_packet(buf, core->mac[VET]) || in e1000e_receive_filter()
1010 e1000x_rx_vlan_filter(core->mac, PKT_GET_VLAN_HDR(buf))) && in e1000e_receive_filter()
1011 e1000x_rx_group_filter(core->mac, buf); in e1000e_receive_filter()
1051 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { in e1000e_read_rx_descr()
1110 if (core->mac[RFCTL] & E1000_RFCTL_ACK_DATA_DIS) { in e1000e_is_tcp_ack()
1152 if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) { in e1000e_build_rx_metadata()
1169 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_DIS)) { in e1000e_build_rx_metadata()
1185 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) { in e1000e_build_rx_metadata()
1312 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { in e1000e_write_rx_descr()
1342 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { in e1000e_pci_dma_write_rx_desc()
1431 e1000x_update_rx_total_stats(core->mac, pkt_type, pkt_size, pkt_fcs_size); in e1000e_update_rx_stats()
1462 if (fragment && (core->mac[RFCTL] & E1000_RFCTL_IPFRSP_DIS)) { in e1000e_do_ps()
1495 size_t total_size = size + e1000x_fcs_len(core->mac); in e1000e_write_packet_to_guest()
1587 (const char *) &fcs_pad, e1000x_fcs_len(core->mac)); in e1000e_write_packet_to_guest()
1643 if (!e1000x_hw_rx_enabled(core->mac)) { in e1000e_receive_internal()
1662 e1000x_inc_reg_if_not_full(core->mac, RUC); in e1000e_receive_internal()
1673 if (e1000x_is_oversized(core->mac, size)) { in e1000e_receive_internal()
1686 e1000x_vlan_enabled(core->mac) ? 0 : -1, in e1000e_receive_internal()
1687 core->mac[VET], 0); in e1000e_receive_internal()
1693 e1000x_fcs_len(core->mac); in e1000e_receive_internal()
1703 if (total_size < core->mac[RSRPD]) { in e1000e_receive_internal()
1708 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS) && in e1000e_receive_internal()
1746 core->mac[CTRL] |= E1000_CTRL_TFCE | E1000_CTRL_RFCE; in e1000e_update_flowctl_status()
1755 e1000x_update_regs_on_link_down(core->mac, core->phy[0]); in e1000e_link_down()
1769 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); in e1000e_set_phy_ctrl()
1779 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); in e1000e_set_phy_oem_bits()
1793 uint32_t old_status = core->mac[STATUS]; in e1000e_core_set_link_status()
1798 e1000x_update_regs_on_link_down(core->mac, core->phy[0]); in e1000e_core_set_link_status()
1802 e1000x_restart_autoneg(core->mac, core->phy[0], in e1000e_core_set_link_status()
1805 e1000x_update_regs_on_link_up(core->mac, core->phy[0]); in e1000e_core_set_link_status()
1810 if (core->mac[STATUS] != old_status) { in e1000e_core_set_link_status()
1821 core->mac[CTRL] = val & ~E1000_CTRL_RST; in e1000e_set_ctrl()
1822 core->mac[CTRL_DUP] = core->mac[CTRL]; in e1000e_set_ctrl()
1839 core->mac[STATUS] |= E1000_STATUS_PHYRA; in e1000e_set_ctrl()
1860 core->mac[RFCTL] = val; in e1000e_set_rfctl()
1877 uint32_t rctl = core->mac[RCTL]; in e1000e_parse_rxbufsize()
1884 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE0_MASK; in e1000e_parse_rxbufsize()
1887 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE1_MASK; in e1000e_parse_rxbufsize()
1890 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE2_MASK; in e1000e_parse_rxbufsize()
1893 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE3_MASK; in e1000e_parse_rxbufsize()
1914 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { in e1000e_calc_rxdesclen()
1926 core->mac[RCTL] = val; in e1000e_set_rx_control()
1927 trace_e1000e_rx_set_rctl(core->mac[RCTL]); in e1000e_set_rx_control()
1958 if (timer->core->mac[timer->delay_reg] != 0) { in e1000e_postpone_interrupt()
1996 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_EIAME) { in e1000e_msix_notify_one()
1997 trace_e1000e_irq_iam_clear_eiame(core->mac[IAM], cause); in e1000e_msix_notify_one()
1998 core->mac[IAM] &= ~cause; in e1000e_msix_notify_one()
2001 trace_e1000e_irq_icr_clear_eiac(core->mac[ICR], core->mac[EIAC]); in e1000e_msix_notify_one()
2003 effective_eiac = core->mac[EIAC] & cause; in e1000e_msix_notify_one()
2005 core->mac[ICR] &= ~effective_eiac; in e1000e_msix_notify_one()
2007 if (!(core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { in e1000e_msix_notify_one()
2008 core->mac[IMS] &= ~effective_eiac; in e1000e_msix_notify_one()
2017 E1000_IVAR_RXQ0(core->mac[IVAR])); in e1000e_msix_notify()
2022 E1000_IVAR_RXQ1(core->mac[IVAR])); in e1000e_msix_notify()
2027 E1000_IVAR_TXQ0(core->mac[IVAR])); in e1000e_msix_notify()
2032 E1000_IVAR_TXQ1(core->mac[IVAR])); in e1000e_msix_notify()
2037 E1000_IVAR_OTHER(core->mac[IVAR])); in e1000e_msix_notify()
2062 E1000_IVAR_RXQ0(core->mac[IVAR])); in e1000e_msix_clear()
2067 E1000_IVAR_RXQ1(core->mac[IVAR])); in e1000e_msix_clear()
2072 E1000_IVAR_TXQ0(core->mac[IVAR])); in e1000e_msix_clear()
2077 E1000_IVAR_TXQ1(core->mac[IVAR])); in e1000e_msix_clear()
2082 E1000_IVAR_OTHER(core->mac[IVAR])); in e1000e_msix_clear()
2089 core->mac[ICR] &= ~E1000_ICR_ASSERTED; in e1000e_fix_icr_asserted()
2090 if (core->mac[ICR]) { in e1000e_fix_icr_asserted()
2091 core->mac[ICR] |= E1000_ICR_ASSERTED; in e1000e_fix_icr_asserted()
2094 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]); in e1000e_fix_icr_asserted()
2101 uint32_t old_causes = core->mac[IMS] & core->mac[ICR]; in e1000e_raise_interrupts()
2105 core->mac[index], core->mac[index] | causes); in e1000e_raise_interrupts()
2107 core->mac[index] |= causes; in e1000e_raise_interrupts()
2111 if (core->mac[ICR] & E1000_ICR_OTHER_CAUSES) { in e1000e_raise_interrupts()
2112 core->mac[ICR] |= E1000_ICR_OTHER; in e1000e_raise_interrupts()
2113 trace_e1000e_irq_add_msi_other(core->mac[ICR]); in e1000e_raise_interrupts()
2127 core->mac[ICS] = core->mac[ICR]; in e1000e_raise_interrupts()
2129 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS], in e1000e_raise_interrupts()
2130 core->mac[ICR], core->mac[IMS]); in e1000e_raise_interrupts()
2132 raised_causes = core->mac[IMS] & core->mac[ICR] & ~old_causes; in e1000e_raise_interrupts()
2153 core->mac[index], core->mac[index] & ~causes); in e1000e_lower_interrupts()
2155 core->mac[index] &= ~causes; in e1000e_lower_interrupts()
2165 core->mac[ICS] = core->mac[ICR]; in e1000e_lower_interrupts()
2167 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS], in e1000e_lower_interrupts()
2168 core->mac[ICR], core->mac[IMS]); in e1000e_lower_interrupts()
2170 if (!(core->mac[IMS] & core->mac[ICR]) && in e1000e_lower_interrupts()
2188 e1000x_update_regs_on_autoneg_done(core->mac, core->phy[0]); in e1000e_autoneg_timer()
2289 val = core->mac[MDIC] | E1000_MDIC_ERROR; in e1000e_set_mdic()
2307 core->mac[MDIC] = val | E1000_MDIC_READY; in e1000e_set_mdic()
2317 core->mac[index] = val & 0xffff; in e1000e_set_rdt()
2326 core->mac[index] &= ~E1000_STATUS_PHYRA; in e1000e_set_status()
2338 core->mac[CTRL_EXT] = val; in e1000e_set_ctrlext()
2346 core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK; in e1000e_set_pbaclr()
2353 if (core->mac[PBACLR] & BIT(i)) { in e1000e_set_pbaclr()
2362 core->mac[FCRTH] = val & 0xFFF8; in e1000e_set_fcrth()
2368 core->mac[FCRTL] = val & 0x8000FFF8; in e1000e_set_fcrtl()
2375 core->mac[index] = val & (BIT(num) - 1); \
2388 core->mac[VET] = val & 0xffff; in e1000e_set_vet()
2389 trace_e1000e_vlan_vet(core->mac[VET]); in e1000e_set_vet()
2395 core->mac[index] = val & E1000_XDLEN_MASK; in e1000e_set_dlen()
2401 core->mac[index] = val & E1000_XDBAL_MASK; in e1000e_set_dbal()
2408 core->mac[index] = val; in e1000e_set_tctl()
2410 if (core->mac[TARC0] & E1000_TARC_ENABLE) { in e1000e_set_tctl()
2415 if (core->mac[TARC1] & E1000_TARC_ENABLE) { in e1000e_set_tctl()
2428 core->mac[index] = val & 0xffff; in e1000e_set_tdt()
2430 if (core->mac[tarc_reg] & E1000_TARC_ENABLE) { in e1000e_set_tdt()
2446 if ((core->mac[ICR] & E1000_ICR_ASSERTED) && in e1000e_set_icr()
2447 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { in e1000e_set_icr()
2449 e1000e_lower_interrupts(core, IMS, core->mac[IAM]); in e1000e_set_icr()
2488 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PBA_CLR) && in e1000e_set_ims()
2494 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_INT_TIMERS_CLEAR_ENA)) { in e1000e_set_ims()
2531 return core->mac[index]; in e1000e_mac_readreg()
2537 trace_e1000e_irq_read_ics(core->mac[ICS]); in e1000e_mac_ics_read()
2538 return core->mac[ICS]; in e1000e_mac_ics_read()
2544 trace_e1000e_irq_read_ims(core->mac[IMS]); in e1000e_mac_ims_read()
2545 return core->mac[IMS]; in e1000e_mac_ims_read()
2551 uint32_t val = core->mac[SWSM]; in e1000e_mac_swsm_read()
2552 core->mac[SWSM] = val | E1000_SWSM_SMBI; in e1000e_mac_swsm_read()
2571 uint32_t ret = core->mac[ICR]; in e1000e_mac_icr_read()
2573 if (core->mac[IMS] == 0) { in e1000e_mac_icr_read()
2583 if (core->mac[ICR] & E1000_ICR_ASSERTED) { in e1000e_mac_icr_read()
2584 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME) { in e1000e_mac_icr_read()
2588 e1000e_lower_interrupts(core, IMS, core->mac[IAM]); in e1000e_mac_icr_read()
2610 if (core->mac[ICR] & core->mac[IMS]) { in e1000e_mac_icr_read()
2611 trace_e1000e_irq_icr_clear_icr_bit_ims(core->mac[ICR], in e1000e_mac_icr_read()
2612 core->mac[IMS]); in e1000e_mac_icr_read()
2623 uint32_t ret = core->mac[index]; in e1000e_mac_read_clr4()
2625 core->mac[index] = 0; in e1000e_mac_read_clr4()
2632 uint32_t ret = core->mac[index]; in e1000e_mac_read_clr8()
2634 core->mac[index] = 0; in e1000e_mac_read_clr8()
2635 core->mac[index - 1] = 0; in e1000e_mac_read_clr8()
2642 uint32_t val = core->mac[CTRL]; in e1000e_get_ctrl()
2658 uint32_t res = core->mac[STATUS]; in e1000e_get_status()
2660 if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE)) { in e1000e_get_status()
2664 if (core->mac[CTRL] & E1000_CTRL_FRCDPX) { in e1000e_get_status()
2665 res |= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0; in e1000e_get_status()
2670 if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) || in e1000e_get_status()
2671 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) { in e1000e_get_status()
2672 switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) { in e1000e_get_status()
2700 return core->mac[index] & ((BIT(11) - 1) | in e1000e_get_tarc()
2710 core->mac[index] = val; in e1000e_mac_writereg()
2718 core->mac[index] = val; in e1000e_mac_setmacaddr()
2720 macaddr[0] = cpu_to_le32(core->mac[RA]); in e1000e_mac_setmacaddr()
2721 macaddr[1] = cpu_to_le32(core->mac[RA + 1]); in e1000e_mac_setmacaddr()
2735 core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits); in e1000e_set_eecd()
2750 core->mac[EERD] = flags | in e1000e_set_eerd()
2767 core->mac[EERD] = flags | in e1000e_set_eewr()
2775 core->mac[RXDCTL] = core->mac[RXDCTL1] = val; in e1000e_set_rxdctl()
2786 core->mac[index] = MAX(interval, E1000E_MIN_XITR); in e1000e_set_itr()
2798 core->mac[index] = MAX(interval, E1000E_MIN_XITR); in e1000e_set_eitr()
2804 if (core->mac[RCTL] & E1000_RCTL_DTYP_MASK) { in e1000e_set_psrctl()
2819 core->mac[PSRCTL] = val; in e1000e_set_psrctl()
2838 core->mac[RXCSUM] = val; in e1000e_set_rxcsum()
2845 uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS; in e1000e_set_gcr()
2846 core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits; in e1000e_set_gcr()
2851 e1000x_timestamp(core->mac, core->timadj, SYSTIML, SYSTIMH); in e1000e_get_systiml()
2852 return core->mac[SYSTIML]; in e1000e_get_systiml()
2857 core->mac[TSYNCRXCTL] &= ~E1000_TSYNCRXCTL_VALID; in e1000e_get_rxsatrh()
2858 return core->mac[RXSATRH]; in e1000e_get_rxsatrh()
2863 core->mac[TSYNCTXCTL] &= ~E1000_TSYNCTXCTL_VALID; in e1000e_get_txstmph()
2864 return core->mac[TXSTMPH]; in e1000e_get_txstmph()
2869 e1000x_set_timinca(core->mac, &core->timadj, val); in e1000e_set_timinca()
2874 core->mac[TIMADJH] = val; in e1000e_set_timadjh()
2875 core->timadj += core->mac[TIMADJL] | ((int64_t)core->mac[TIMADJH] << 32); in e1000e_set_timadjh()
3241 * MAC registers that have aliases, with the indication of not fully
3467 core->mac[i] = i < ARRAY_SIZE(e1000e_mac_reg_init) ? in e1000e_reset()
3477 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac); in e1000e_reset()
3520 * to link status bit in core.mac[STATUS]. in e1000e_core_post_load()
3522 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0; in e1000e_core_post_load()