hw/net/e1000e_core.c

70 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val);
1755 e1000e_set_phy_ctrl(E1000ECore *core, int index, uint16_t val)
1758     core->phy[0][MII_BMCR] = val & ~(0x3f |
1762     if ((val & MII_BMCR_ANRESTART) &&
1769 e1000e_set_phy_oem_bits(E1000ECore *core, int index, uint16_t val)
1771     core->phy[0][PHY_OEM_BITS] = val & ~BIT(10);
1773     if (val & BIT(10)) {
1779 e1000e_set_phy_page(E1000ECore *core, int index, uint16_t val)
1781     core->phy[0][PHY_PAGE] = val & PHY_PAGE_RW_MASK;
1811 e1000e_set_ctrl(E1000ECore *core, int index, uint32_t val)
1813     trace_e1000e_core_ctrl_write(index, val);
1816     core->mac[CTRL] = val & ~E1000_CTRL_RST;
1820         !!(val & E1000_CTRL_ASDE),
1821         (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT,
1822         !!(val & E1000_CTRL_FRCSPD),
1823         !!(val & E1000_CTRL_FRCDPX),
1824         !!(val & E1000_CTRL_RFCE),
1825         !!(val & E1000_CTRL_TFCE));
1827     if (val & E1000_CTRL_RST) {
1832     if (val & E1000_CTRL_PHY_RST) {
1839 e1000e_set_rfctl(E1000ECore *core, int index, uint32_t val)
1841     trace_e1000e_rx_set_rfctl(val);
1843     if (!(val & E1000_RFCTL_ISCSI_DIS)) {
1847     if (!(val & E1000_RFCTL_NFSW_DIS)) {
1851     if (!(val & E1000_RFCTL_NFSR_DIS)) {
1855     core->mac[RFCTL] = val;
1919 e1000e_set_rx_control(E1000ECore *core, int index, uint32_t val)
1921     core->mac[RCTL] = val;
1924     if (val & E1000_RCTL_EN) {
1927         core->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1 +
2172 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val)
2174     val |= e1000e_intmgr_collect_delayed_causes(core);
2175     e1000e_raise_interrupts(core, ICR, val);
2277 e1000e_set_mdic(E1000ECore *core, int index, uint32_t val)
2279     uint32_t data = val & E1000_MDIC_DATA_MASK;
2280     uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
2283     if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) { /* phy # */
2284         val = core->mac[MDIC] | E1000_MDIC_ERROR;
2285     } else if (val & E1000_MDIC_OP_READ) {
2288             val |= E1000_MDIC_ERROR;
2290             val = (val ^ data) | core->phy[page][addr];
2291             trace_e1000e_core_mdic_read(page, addr, val);
2293     } else if (val & E1000_MDIC_OP_WRITE) {
2296             val |= E1000_MDIC_ERROR;
2302     core->mac[MDIC] = val | E1000_MDIC_READY;
2304     if (val & E1000_MDIC_INT_EN) {
2310 e1000e_set_rdt(E1000ECore *core, int index, uint32_t val)
2312     core->mac[index] = val & 0xffff;
2313     trace_e1000e_rx_set_rdt(e1000e_mq_queue_idx(RDT0, index), val);
2318 e1000e_set_status(E1000ECore *core, int index, uint32_t val)
2320     if ((val & E1000_STATUS_PHYRA) == 0) {
2326 e1000e_set_ctrlext(E1000ECore *core, int index, uint32_t val)
2328     trace_e1000e_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK),
2329                                      !!(val & E1000_CTRL_EXT_SPD_BYPS));
2332     val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST);
2333     core->mac[CTRL_EXT] = val;
2337 e1000e_set_pbaclr(E1000ECore *core, int index, uint32_t val)
2341     core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK;
2355 e1000e_set_fcrth(E1000ECore *core, int index, uint32_t val)
2357     core->mac[FCRTH] = val & 0xFFF8;
2361 e1000e_set_fcrtl(E1000ECore *core, int index, uint32_t val)
2363     core->mac[FCRTL] = val & 0x8000FFF8;
2368     e1000e_set_##num##bit(E1000ECore *core, int index, uint32_t val) \
2370         core->mac[index] = val & (BIT(num) - 1);                     \
2381 e1000e_set_vet(E1000ECore *core, int index, uint32_t val)
2383     core->mac[VET] = val & 0xffff;
2388 e1000e_set_dlen(E1000ECore *core, int index, uint32_t val)
2390     core->mac[index] = val & E1000_XDLEN_MASK;
2394 e1000e_set_dbal(E1000ECore *core, int index, uint32_t val)
2396     core->mac[index] = val & E1000_XDBAL_MASK;
2400 e1000e_set_tctl(E1000ECore *core, int index, uint32_t val)
2403     core->mac[index] = val;
2417 e1000e_set_tdt(E1000ECore *core, int index, uint32_t val)
2423     core->mac[index] = val & 0xffff;
2432 e1000e_set_ics(E1000ECore *core, int index, uint32_t val)
2434     trace_e1000e_irq_write_ics(val);
2435     e1000e_set_interrupt_cause(core, val);
2439 e1000e_set_icr(E1000ECore *core, int index, uint32_t val)
2451     if (val & E1000_ICR_OTHER) {
2452         val |= E1000_ICR_OTHER_CAUSES;
2454     e1000e_lower_interrupts(core, ICR, val);
2458 e1000e_set_imc(E1000ECore *core, int index, uint32_t val)
2460     trace_e1000e_irq_ims_clear_set_imc(val);
2461     e1000e_lower_interrupts(core, IMS, val);
2465 e1000e_set_ims(E1000ECore *core, int index, uint32_t val)
2480     uint32_t valid_val = val & ims_valid_mask;
2490         trace_e1000e_irq_fire_all_timers(val);
2498 e1000e_set_rdtr(E1000ECore *core, int index, uint32_t val)
2500     e1000e_set_16bit(core, index, val);
2502     if ((val & E1000_RDTR_FPD) && (core->rdtr.running)) {
2511 e1000e_set_tidv(E1000ECore *core, int index, uint32_t val)
2513     e1000e_set_16bit(core, index, val);
2515     if ((val & E1000_TIDV_FPD) && (core->tidv.running)) {
2546     uint32_t val = core->mac[SWSM];
2547     core->mac[SWSM] = val | E1000_SWSM_SMBI;
2548     return val;
2637     uint32_t val = core->mac[CTRL];
2640         !!(val & E1000_CTRL_ASDE),
2641         (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT,
2642         !!(val & E1000_CTRL_FRCSPD),
2643         !!(val & E1000_CTRL_FRCDPX),
2644         !!(val & E1000_CTRL_RFCE),
2645         !!(val & E1000_CTRL_TFCE));
2647     return val;
2703 e1000e_mac_writereg(E1000ECore *core, int index, uint32_t val)
2705     core->mac[index] = val;
2709 e1000e_mac_setmacaddr(E1000ECore *core, int index, uint32_t val)
2713     core->mac[index] = val;
2724 e1000e_set_eecd(E1000ECore *core, int index, uint32_t val)
2730     core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits);
2734 e1000e_set_eerd(E1000ECore *core, int index, uint32_t val)
2736     uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK;
2740     if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) {
2751 e1000e_set_eewr(E1000ECore *core, int index, uint32_t val)
2753     uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK;
2754     uint32_t data = (val >> E1000_EERW_DATA_SHIFT) & E1000_EERW_DATA_MASK;
2757     if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) {
2768 e1000e_set_rxdctl(E1000ECore *core, int index, uint32_t val)
2770     core->mac[RXDCTL] = core->mac[RXDCTL1] = val;
2774 e1000e_set_itr(E1000ECore *core, int index, uint32_t val)
2776     uint32_t interval = val & 0xffff;
2778     trace_e1000e_irq_itr_set(val);
2785 e1000e_set_eitr(E1000ECore *core, int index, uint32_t val)
2787     uint32_t interval = val & 0xffff;
2790     trace_e1000e_irq_eitr_set(eitr_num, val);
2797 e1000e_set_psrctl(E1000ECore *core, int index, uint32_t val)
2801         if ((val & E1000_PSRCTL_BSIZE0_MASK) == 0) {
2807         if ((val & E1000_PSRCTL_BSIZE1_MASK) == 0) {
2814     core->mac[PSRCTL] = val;
2831 e1000e_set_rxcsum(E1000ECore *core, int index, uint32_t val)
2833     core->mac[RXCSUM] = val;
2838 e1000e_set_gcr(E1000ECore *core, int index, uint32_t val)
2841     core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits;
2862 static void e1000e_set_timinca(E1000ECore *core, int index, uint32_t val)
2864     e1000x_set_timinca(core->mac, &core->timadj, val);
2867 static void e1000e_set_timadjh(E1000ECore *core, int index, uint32_t val)
2869     core->mac[TIMADJH] = val;
3268 e1000e_core_write(E1000ECore *core, hwaddr addr, uint64_t val, unsigned size)
3276         trace_e1000e_core_write(index << 2, size, val);
3277         e1000e_macreg_writeops[index](core, index, val);
3279         trace_e1000e_wrn_regs_write_ro(index << 2, size, val);
3281         trace_e1000e_wrn_regs_write_unknown(index << 2, size, val);
3288     uint64_t val;
3295         val = e1000e_macreg_readops[index](core, index);
3296         trace_e1000e_core_read(index << 2, size, val);
3297         return val;