hw/net/e1000_regs.h

41 #define E1000_RDBAL1   0x02900  /* RX Descriptor Base Address Low (1) - RW */
42 #define E1000_RDBAH1   0x02904  /* RX Descriptor Base Address High (1) - RW */
43 #define E1000_RDLEN1   0x02908  /* RX Descriptor Length (1) - RW */
44 #define E1000_RDH1     0x02910  /* RX Descriptor Head (1) - RW */
45 #define E1000_RDT1     0x02918  /* RX Descriptor Tail (1) - RW */
66 #define E1000_RDBAL    0x02800  /* RX Descriptor Base Address Low - RW */
67 #define E1000_RDBAH    0x02804  /* RX Descriptor Base Address High - RW */
68 #define E1000_RDLEN    0x02808  /* RX Descriptor Length - RW */
69 #define E1000_RDH      0x02810  /* RX Descriptor Head - RW */
70 #define E1000_RDT      0x02818  /* RX Descriptor Tail - RW */
84 #define E1000_RXDCTL   0x02828  /* RX Descriptor Control queue 0 - RW */
85 #define E1000_RXDCTL1  0x02928  /* RX Descriptor Control queue 1 - RW */
90 #define E1000_TDBAL    0x03800  /* TX Descriptor Base Address Low - RW */
92 #define E1000_TDBAH    0x03804  /* TX Descriptor Base Address High - RW */
94 #define E1000_TDLEN    0x03808  /* TX Descriptor Length - RW */
96 #define E1000_TDH      0x03810  /* TX Descriptor Head - RW */
102 #define E1000_TXDCTL   0x03828  /* TX Descriptor Control - RW */
111 #define E1000_TXDCTL1  0x03928  /* TX Descriptor Control (1) - RW */
275 /* Transmit Descriptor */
277     uint64_t buffer_addr;       /* Address of the descriptor's data buffer */
283             uint8_t cmd;        /* Descriptor control */
289             uint8_t status;     /* Descriptor status */