Lines Matching refs:DBGOUT

59 #define DBGOUT(what, fmt, ...) do { \  macro
64 #define DBGOUT(what, fmt, ...) do {} while (0) macro
354 DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR], in set_ics()
428 DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT], in set_rx_control()
443 DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr); in set_mdic()
445 DBGOUT(MDIC, "MDIC read reg %x unhandled\n", addr); in set_mdic()
450 DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data); in set_mdic()
452 DBGOUT(MDIC, "MDIC write reg %x unhandled\n", addr); in set_mdic()
474 DBGOUT(EEPROM, "reading eeprom bit %d (reading %d)\n", in get_eecd()
514 DBGOUT(EEPROM, "eeprom bitnum in %d out %d, reading %d\n", in set_eecd()
583 DBGOUT(TXSUM, "frames %d size %d ipcss %d\n", in xmit_seg()
594 DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", props->tcp, css, len); in xmit_seg()
762 DBGOUT(TX, "tx disabled\n"); in start_xmit()
776 DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH], in start_xmit()
792 DBGOUT(TXERR, "TDH wraparound @%x, TDT %x, TDLEN %x\n", in start_xmit()
981 DBGOUT(RX, "Null RX descriptor!!\n"); in e1000_receive_iov()
993 DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n", in e1000_receive_iov()
1036 DBGOUT(INTERRUPT, "ICR read: %x\n", ret); in mac_icr_read()
1112 DBGOUT(INTERRUPT, "set_icr %x\n", val); in set_icr()
1274 DBGOUT(GENERAL, "Writing to register at offset: 0x%08x. " in e1000_mmio_write()
1279 DBGOUT(MMIO, "MMIO write attempt to disabled reg. addr=0x%08x\n", in e1000_mmio_write()
1283 DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04"PRIx64"\n", in e1000_mmio_write()
1286 DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08"PRIx64"\n", in e1000_mmio_write()
1301 DBGOUT(GENERAL, "Reading register at offset: 0x%08x. " in e1000_mmio_read()
1306 DBGOUT(MMIO, "MMIO read attempt of disabled reg. addr=0x%08x\n", in e1000_mmio_read()
1310 DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2); in e1000_mmio_read()