Lines Matching +full:tp +full:- +full:link
31 #include "hw/qdev-properties.h"
144 #define chkflag(x) (s->compat_flags & E1000_FLAG_##x)
152 #define TYPE_E1000_BASE "e1000-base"
161 e1000x_update_regs_on_link_up(s->mac_reg, s->phy_reg); in DECLARE_OBJ_CHECKERS()
164 qemu_flush_queued_packets(qemu_get_queue(s->nic)); in DECLARE_OBJ_CHECKERS()
170 e1000x_update_regs_on_autoneg_done(s->mac_reg, s->phy_reg); in e1000_autoneg_done()
173 qemu_flush_queued_packets(qemu_get_queue(s->nic)); in e1000_autoneg_done()
179 return (s->phy_reg[MII_BMCR] & MII_BMCR_AUTOEN); in have_autoneg()
185 /* bits 0-5 reserved; MII_BMCR_[ANRESTART,RESET] are self clearing */ in set_phy_ctrl()
186 s->phy_reg[MII_BMCR] = val & ~(0x3f | in set_phy_ctrl()
191 * QEMU 1.3 does not support link auto-negotiation emulation, so if we in set_phy_ctrl()
192 * migrate during auto negotiation, after migration the link will be in set_phy_ctrl()
196 e1000x_restart_autoneg(s->mac_reg, s->phy_reg, s->autoneg_timer); in set_phy_ctrl()
224 MII_BMSR_LINK_ST | /* link initially up */
281 s->mac_reg[ICR] = val; in set_interrupt_cause()
285 * The spec says that the ICS register is write-only. However in practice, in set_interrupt_cause()
291 s->mac_reg[ICS] = val; in set_interrupt_cause()
293 pending_ints = (s->mac_reg[IMS] & s->mac_reg[ICR]); in set_interrupt_cause()
294 if (!s->mit_irq_level && pending_ints) { in set_interrupt_cause()
298 * (s->mit_timer_on == 1). in set_interrupt_cause()
304 if (s->mit_timer_on) { in set_interrupt_cause()
314 if (s->mit_ide && in set_interrupt_cause()
316 mit_update_delay(&mit_delay, s->mac_reg[TADV] * 4); in set_interrupt_cause()
318 if (s->mac_reg[RDTR] && (pending_ints & E1000_ICS_RXT0)) { in set_interrupt_cause()
319 mit_update_delay(&mit_delay, s->mac_reg[RADV] * 4); in set_interrupt_cause()
321 mit_update_delay(&mit_delay, s->mac_reg[ITR]); in set_interrupt_cause()
331 s->mit_timer_on = 1; in set_interrupt_cause()
332 timer_mod(s->mit_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + in set_interrupt_cause()
334 s->mit_ide = 0; in set_interrupt_cause()
337 s->mit_irq_level = (pending_ints != 0); in set_interrupt_cause()
338 pci_set_irq(d, s->mit_irq_level); in set_interrupt_cause()
346 s->mit_timer_on = 0; in e1000_mit_timer()
348 set_interrupt_cause(s, 0, s->mac_reg[ICR]); in e1000_mit_timer()
354 DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR], in set_ics()
355 s->mac_reg[IMS]); in set_ics()
356 set_interrupt_cause(s, 0, val | s->mac_reg[ICR]); in set_ics()
363 if (!qemu_get_queue(s->nic)->link_down) { in e1000_autoneg_timer()
365 set_ics(s, 0, E1000_ICS_LSC); /* signal link status change to guest */ in e1000_autoneg_timer()
380 uint8_t *macaddr = d->conf.macaddr.a; in e1000_reset_hold()
382 timer_del(d->autoneg_timer); in e1000_reset_hold()
383 timer_del(d->mit_timer); in e1000_reset_hold()
384 timer_del(d->flush_queue_timer); in e1000_reset_hold()
385 d->mit_timer_on = 0; in e1000_reset_hold()
386 d->mit_irq_level = 0; in e1000_reset_hold()
387 d->mit_ide = 0; in e1000_reset_hold()
388 memset(d->phy_reg, 0, sizeof d->phy_reg); in e1000_reset_hold()
389 memcpy(d->phy_reg, phy_reg_init, sizeof phy_reg_init); in e1000_reset_hold()
390 d->phy_reg[MII_PHYID2] = edc->phy_id2; in e1000_reset_hold()
391 memset(d->mac_reg, 0, sizeof d->mac_reg); in e1000_reset_hold()
392 memcpy(d->mac_reg, mac_reg_init, sizeof mac_reg_init); in e1000_reset_hold()
393 d->rxbuf_min_shift = 1; in e1000_reset_hold()
394 memset(&d->tx, 0, sizeof d->tx); in e1000_reset_hold()
396 if (qemu_get_queue(d->nic)->link_down) { in e1000_reset_hold()
397 e1000x_update_regs_on_link_down(d->mac_reg, d->phy_reg); in e1000_reset_hold()
400 e1000x_reset_mac_addr(d->nic, d->mac_reg, macaddr); in e1000_reset_hold()
403 d->mac_reg[VET] = ETH_P_VLAN; in e1000_reset_hold()
411 s->mac_reg[CTRL] = val & ~E1000_CTRL_RST; in set_ctrl()
419 qemu_flush_queued_packets(qemu_get_queue(s->nic)); in e1000_flush_queue_timer()
425 s->mac_reg[RCTL] = val; in set_rx_control()
426 s->rxbuf_size = e1000x_rxbufsize(val); in set_rx_control()
427 s->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1; in set_rx_control()
428 DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT], in set_rx_control()
429 s->mac_reg[RCTL]); in set_rx_control()
430 timer_mod(s->flush_queue_timer, in set_rx_control()
441 val = s->mac_reg[MDIC] | E1000_MDIC_ERROR; in set_mdic()
448 val = (val ^ data) | s->phy_reg[addr]; in set_mdic()
458 s->phy_reg[addr] = data; in set_mdic()
462 s->mac_reg[MDIC] = val | E1000_MDIC_READY; in set_mdic()
472 uint32_t ret = E1000_EECD_PRES|E1000_EECD_GNT | s->eecd_state.old_eecd; in get_eecd()
475 s->eecd_state.bitnum_out, s->eecd_state.reading); in get_eecd()
476 if (!s->eecd_state.reading || in get_eecd()
477 ((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >> in get_eecd()
478 ((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1) in get_eecd()
486 uint32_t oldval = s->eecd_state.old_eecd; in set_eecd()
488 s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS | in set_eecd()
494 s->eecd_state.val_in = 0; in set_eecd()
495 s->eecd_state.bitnum_in = 0; in set_eecd()
496 s->eecd_state.bitnum_out = 0; in set_eecd()
497 s->eecd_state.reading = 0; in set_eecd()
503 s->eecd_state.bitnum_out++; in set_eecd()
506 s->eecd_state.val_in <<= 1; in set_eecd()
508 s->eecd_state.val_in |= 1; in set_eecd()
509 if (++s->eecd_state.bitnum_in == 9 && !s->eecd_state.reading) { in set_eecd()
510 s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1; in set_eecd()
511 s->eecd_state.reading = (((s->eecd_state.val_in >> 6) & 7) == in set_eecd()
515 s->eecd_state.bitnum_in, s->eecd_state.bitnum_out, in set_eecd()
516 s->eecd_state.reading); in set_eecd()
522 unsigned int index, r = s->mac_reg[EERD] & ~E1000_EEPROM_RW_REG_START; in flash_eerd_read()
524 if ((s->mac_reg[EERD] & E1000_EEPROM_RW_REG_START) == 0) in flash_eerd_read()
525 return (s->mac_reg[EERD]); in flash_eerd_read()
530 return ((s->eeprom_data[index] << E1000_EEPROM_RW_REG_DATA) | in flash_eerd_read()
541 if (sloc < n-1) { in putsum()
542 sum = net_checksum_add(n-css, data+css); in putsum()
551 e1000x_inc_reg_if_not_full(s->mac_reg, BPTC); in inc_tx_bcast_or_mcast_count()
553 e1000x_inc_reg_if_not_full(s->mac_reg, MPTC); in inc_tx_bcast_or_mcast_count()
563 NetClientState *nc = qemu_get_queue(s->nic); in e1000_send_packet()
564 if (s->phy_reg[MII_BMCR] & MII_BMCR_LOOPBACK) { in e1000_send_packet()
570 e1000x_increase_size_stats(s->mac_reg, PTCregs, size + 4); in e1000_send_packet()
577 unsigned int frames = s->tx.tso_frames, css, sofar; in xmit_seg()
578 struct e1000_tx *tp = &s->tx; in xmit_seg() local
579 struct e1000x_txd_props *props = tp->cptse ? &tp->tso_props : &tp->props; in xmit_seg()
581 if (tp->cptse) { in xmit_seg()
582 css = props->ipcss; in xmit_seg()
584 frames, tp->size, css); in xmit_seg()
585 if (props->ip) { /* IPv4 */ in xmit_seg()
586 stw_be_p(tp->data+css+2, tp->size - css); in xmit_seg()
587 stw_be_p(tp->data+css+4, in xmit_seg()
588 lduw_be_p(tp->data + css + 4) + frames); in xmit_seg()
590 stw_be_p(tp->data+css+4, tp->size - css); in xmit_seg()
592 css = props->tucss; in xmit_seg()
593 len = tp->size - css; in xmit_seg()
594 DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", props->tcp, css, len); in xmit_seg()
595 if (props->tcp) { in xmit_seg()
596 sofar = frames * props->mss; in xmit_seg()
597 stl_be_p(tp->data+css+4, ldl_be_p(tp->data+css+4)+sofar); /* seq */ in xmit_seg()
598 if (props->paylen - sofar > props->mss) { in xmit_seg()
599 tp->data[css + 13] &= ~9; /* PSH, FIN */ in xmit_seg()
601 e1000x_inc_reg_if_not_full(s->mac_reg, TSCTC); in xmit_seg()
604 stw_be_p(tp->data+css+4, len); in xmit_seg()
606 if (tp->sum_needed & E1000_TXD_POPTS_TXSM) { in xmit_seg()
608 // add pseudo-header length before checksum calculation in xmit_seg()
609 void *sp = tp->data + props->tucso; in xmit_seg()
615 tp->tso_frames++; in xmit_seg()
618 if (tp->sum_needed & E1000_TXD_POPTS_TXSM) { in xmit_seg()
619 putsum(tp->data, tp->size, props->tucso, props->tucss, props->tucse); in xmit_seg()
621 if (tp->sum_needed & E1000_TXD_POPTS_IXSM) { in xmit_seg()
622 putsum(tp->data, tp->size, props->ipcso, props->ipcss, props->ipcse); in xmit_seg()
624 if (tp->vlan_needed) { in xmit_seg()
625 memmove(tp->vlan, tp->data, 4); in xmit_seg()
626 memmove(tp->data, tp->data + 4, 8); in xmit_seg()
627 memcpy(tp->data + 8, tp->vlan_header, 4); in xmit_seg()
628 e1000_send_packet(s, tp->vlan, tp->size + 4); in xmit_seg()
630 e1000_send_packet(s, tp->data, tp->size); in xmit_seg()
633 e1000x_inc_reg_if_not_full(s->mac_reg, TPT); in xmit_seg()
634 e1000x_grow_8reg_if_not_full(s->mac_reg, TOTL, s->tx.size + 4); in xmit_seg()
635 e1000x_inc_reg_if_not_full(s->mac_reg, GPTC); in xmit_seg()
636 e1000x_grow_8reg_if_not_full(s->mac_reg, GOTCL, s->tx.size + 4); in xmit_seg()
643 uint32_t txd_lower = le32_to_cpu(dp->lower.data); in process_tx_desc()
649 struct e1000_tx *tp = &s->tx; in process_tx_desc() local
651 s->mit_ide |= (txd_lower & E1000_TXD_CMD_IDE); in process_tx_desc()
653 if (le32_to_cpu(xp->cmd_and_length) & E1000_TXD_CMD_TSE) { in process_tx_desc()
654 e1000x_read_tx_ctx_descr(xp, &tp->tso_props); in process_tx_desc()
655 s->use_tso_for_migration = 1; in process_tx_desc()
656 tp->tso_frames = 0; in process_tx_desc()
658 e1000x_read_tx_ctx_descr(xp, &tp->props); in process_tx_desc()
659 s->use_tso_for_migration = 0; in process_tx_desc()
664 if (tp->size == 0) { in process_tx_desc()
665 tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8; in process_tx_desc()
667 tp->cptse = (txd_lower & E1000_TXD_CMD_TSE) ? 1 : 0; in process_tx_desc()
670 tp->cptse = 0; in process_tx_desc()
673 if (e1000x_vlan_enabled(s->mac_reg) && in process_tx_desc()
675 (tp->cptse || txd_lower & E1000_TXD_CMD_EOP)) { in process_tx_desc()
676 tp->vlan_needed = 1; in process_tx_desc()
677 stw_be_p(tp->vlan_header, in process_tx_desc()
678 le16_to_cpu(s->mac_reg[VET])); in process_tx_desc()
679 stw_be_p(tp->vlan_header + 2, in process_tx_desc()
680 le16_to_cpu(dp->upper.fields.special)); in process_tx_desc()
683 addr = le64_to_cpu(dp->buffer_addr); in process_tx_desc()
684 if (tp->cptse) { in process_tx_desc()
685 msh = tp->tso_props.hdr_len + tp->tso_props.mss; in process_tx_desc()
688 if (tp->size >= msh) { in process_tx_desc()
691 if (tp->size + bytes > msh) in process_tx_desc()
692 bytes = msh - tp->size; in process_tx_desc()
694 bytes = MIN(sizeof(tp->data) - tp->size, bytes); in process_tx_desc()
695 pci_dma_read(d, addr, tp->data + tp->size, bytes); in process_tx_desc()
696 sz = tp->size + bytes; in process_tx_desc()
697 if (sz >= tp->tso_props.hdr_len in process_tx_desc()
698 && tp->size < tp->tso_props.hdr_len) { in process_tx_desc()
699 memmove(tp->header, tp->data, tp->tso_props.hdr_len); in process_tx_desc()
701 tp->size = sz; in process_tx_desc()
705 memmove(tp->data, tp->header, tp->tso_props.hdr_len); in process_tx_desc()
706 tp->size = tp->tso_props.hdr_len; in process_tx_desc()
708 split_size -= bytes; in process_tx_desc()
711 split_size = MIN(sizeof(tp->data) - tp->size, split_size); in process_tx_desc()
712 pci_dma_read(d, addr, tp->data + tp->size, split_size); in process_tx_desc()
713 tp->size += split_size; in process_tx_desc()
719 if (!(tp->cptse && tp->size < tp->tso_props.hdr_len)) { in process_tx_desc()
722 tp->tso_frames = 0; in process_tx_desc()
723 tp->sum_needed = 0; in process_tx_desc()
724 tp->vlan_needed = 0; in process_tx_desc()
725 tp->size = 0; in process_tx_desc()
726 tp->cptse = 0; in process_tx_desc()
733 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data); in txdesc_writeback()
737 txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) & in txdesc_writeback()
739 dp->upper.data = cpu_to_le32(txd_upper); in txdesc_writeback()
740 pci_dma_write(d, base + ((char *)&dp->upper - (char *)dp), in txdesc_writeback()
741 &dp->upper, sizeof(dp->upper)); in txdesc_writeback()
747 uint64_t bah = s->mac_reg[TDBAH]; in tx_desc_base()
748 uint64_t bal = s->mac_reg[TDBAL] & ~0xf; in tx_desc_base()
759 uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE; in start_xmit()
761 if (!(s->mac_reg[TCTL] & E1000_TCTL_EN)) { in start_xmit()
766 if (s->tx.busy) { in start_xmit()
769 s->tx.busy = true; in start_xmit()
771 while (s->mac_reg[TDH] != s->mac_reg[TDT]) { in start_xmit()
773 sizeof(struct e1000_tx_desc) * s->mac_reg[TDH]; in start_xmit()
776 DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH], in start_xmit()
783 if (++s->mac_reg[TDH] * sizeof(desc) >= s->mac_reg[TDLEN]) in start_xmit()
784 s->mac_reg[TDH] = 0; in start_xmit()
790 if (s->mac_reg[TDH] == tdh_start || in start_xmit()
791 tdh_start >= s->mac_reg[TDLEN] / sizeof(desc)) { in start_xmit()
793 tdh_start, s->mac_reg[TDT], s->mac_reg[TDLEN]); in start_xmit()
797 s->tx.busy = false; in start_xmit()
804 return (!e1000x_is_vlan_packet(buf, s->mac_reg[VET]) || in receive_filter()
805 e1000x_rx_vlan_filter(s->mac_reg, PKT_GET_VLAN_HDR(buf))) && in receive_filter()
806 e1000x_rx_group_filter(s->mac_reg, buf); in receive_filter()
813 uint32_t old_status = s->mac_reg[STATUS]; in e1000_set_link_status()
815 if (nc->link_down) { in e1000_set_link_status()
816 e1000x_update_regs_on_link_down(s->mac_reg, s->phy_reg); in e1000_set_link_status()
819 !(s->phy_reg[MII_BMSR] & MII_BMSR_AN_COMP)) { in e1000_set_link_status()
820 e1000x_restart_autoneg(s->mac_reg, s->phy_reg, s->autoneg_timer); in e1000_set_link_status()
826 if (s->mac_reg[STATUS] != old_status) in e1000_set_link_status()
833 /* Fast-path short packets */ in e1000_has_rxbufs()
834 if (total_size <= s->rxbuf_size) { in e1000_has_rxbufs()
835 return s->mac_reg[RDH] != s->mac_reg[RDT]; in e1000_has_rxbufs()
837 if (s->mac_reg[RDH] < s->mac_reg[RDT]) { in e1000_has_rxbufs()
838 bufs = s->mac_reg[RDT] - s->mac_reg[RDH]; in e1000_has_rxbufs()
839 } else if (s->mac_reg[RDH] > s->mac_reg[RDT]) { in e1000_has_rxbufs()
840 bufs = s->mac_reg[RDLEN] / sizeof(struct e1000_rx_desc) + in e1000_has_rxbufs()
841 s->mac_reg[RDT] - s->mac_reg[RDH]; in e1000_has_rxbufs()
845 return total_size <= bufs * s->rxbuf_size; in e1000_has_rxbufs()
853 return e1000x_rx_ready(&s->parent_obj, s->mac_reg) && in e1000_can_receive()
854 e1000_has_rxbufs(s, 1) && !timer_pending(s->flush_queue_timer); in e1000_can_receive()
859 uint64_t bah = s->mac_reg[RDBAH]; in rx_desc_base()
860 uint64_t bal = s->mac_reg[RDBAL] & ~0xf; in rx_desc_base()
868 trace_e1000_receiver_overrun(size, s->mac_reg[RDH], s->mac_reg[RDT]); in e1000_receiver_overrun()
869 e1000x_inc_reg_if_not_full(s->mac_reg, RNBC); in e1000_receiver_overrun()
870 e1000x_inc_reg_if_not_full(s->mac_reg, MPC); in e1000_receiver_overrun()
886 uint8_t *filter_buf = iov->iov_base; in e1000_receive_iov()
894 if (!e1000x_hw_rx_enabled(s->mac_reg)) { in e1000_receive_iov()
895 return -1; in e1000_receive_iov()
898 if (timer_pending(s->flush_queue_timer)) { in e1000_receive_iov()
902 if (iov->iov_len < MAXIMUM_ETHERNET_HDR_LEN) { in e1000_receive_iov()
909 if (e1000x_is_oversized(s->mac_reg, size)) { in e1000_receive_iov()
917 if (e1000x_vlan_enabled(s->mac_reg) && in e1000_receive_iov()
918 e1000x_is_vlan_packet(filter_buf, le16_to_cpu(s->mac_reg[VET]))) { in e1000_receive_iov()
921 if (filter_buf == iov->iov_base) { in e1000_receive_iov()
925 while (iov->iov_len <= iov_ofs) { in e1000_receive_iov()
926 iov_ofs -= iov->iov_len; in e1000_receive_iov()
931 size -= 4; in e1000_receive_iov()
935 rdh_start = s->mac_reg[RDH]; in e1000_receive_iov()
937 total_size = size + e1000x_fcs_len(s->mac_reg); in e1000_receive_iov()
940 return -1; in e1000_receive_iov()
943 desc_size = total_size - desc_offset; in e1000_receive_iov()
944 if (desc_size > s->rxbuf_size) { in e1000_receive_iov()
945 desc_size = s->rxbuf_size; in e1000_receive_iov()
947 base = rx_desc_base(s) + sizeof(desc) * s->mac_reg[RDH]; in e1000_receive_iov()
955 size_t copy_size = size - desc_offset; in e1000_receive_iov()
956 if (copy_size > s->rxbuf_size) { in e1000_receive_iov()
957 copy_size = s->rxbuf_size; in e1000_receive_iov()
960 iov_copy = MIN(copy_size, iov->iov_len - iov_ofs); in e1000_receive_iov()
961 pci_dma_write(d, ba, iov->iov_base + iov_ofs, iov_copy); in e1000_receive_iov()
962 copy_size -= iov_copy; in e1000_receive_iov()
965 if (iov_ofs == iov->iov_len) { in e1000_receive_iov()
988 if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN]) in e1000_receive_iov()
989 s->mac_reg[RDH] = 0; in e1000_receive_iov()
991 if (s->mac_reg[RDH] == rdh_start || in e1000_receive_iov()
992 rdh_start >= s->mac_reg[RDLEN] / sizeof(desc)) { in e1000_receive_iov()
994 rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]); in e1000_receive_iov()
996 return -1; in e1000_receive_iov()
1000 e1000x_update_rx_total_stats(s->mac_reg, pkt_type, size, total_size); in e1000_receive_iov()
1003 if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH]) in e1000_receive_iov()
1004 rdt += s->mac_reg[RDLEN] / sizeof(desc); in e1000_receive_iov()
1005 if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) <= s->mac_reg[RDLEN] >> in e1000_receive_iov()
1006 s->rxbuf_min_shift) in e1000_receive_iov()
1028 return s->mac_reg[index]; in mac_readreg()
1034 uint32_t ret = s->mac_reg[ICR]; in mac_icr_read()
1044 uint32_t ret = s->mac_reg[index]; in mac_read_clr4()
1046 s->mac_reg[index] = 0; in mac_read_clr4()
1053 uint32_t ret = s->mac_reg[index]; in mac_read_clr8()
1055 s->mac_reg[index] = 0; in mac_read_clr8()
1056 s->mac_reg[index-1] = 0; in mac_read_clr8()
1065 s->mac_reg[index] = val; in mac_writereg()
1068 macaddr[0] = cpu_to_le32(s->mac_reg[RA]); in mac_writereg()
1069 macaddr[1] = cpu_to_le32(s->mac_reg[RA + 1]); in mac_writereg()
1070 qemu_format_nic_info_str(qemu_get_queue(s->nic), (uint8_t *)macaddr); in mac_writereg()
1077 s->mac_reg[index] = val & 0xffff; in set_rdt()
1079 qemu_flush_queued_packets(qemu_get_queue(s->nic)); in set_rdt()
1087 s->mac_reg[index] = val & (BIT(num) - 1); \
1098 s->mac_reg[index] = val & 0xfff80; in set_dlen()
1104 s->mac_reg[index] = val; in set_tctl()
1105 s->mac_reg[TDT] &= 0xffff; in set_tctl()
1113 set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val); in set_icr()
1119 s->mac_reg[IMS] &= ~val; in set_imc()
1126 s->mac_reg[IMS] |= val; in set_ims()
1173 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = &mac_readreg,
1174 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = &mac_readreg,
1205 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = &mac_writereg,
1206 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = &mac_writereg,
1217 * f - flag bits (up to 6 possible flags)
1218 * n - flag needed
1219 * p - partially implenented */
1272 || (s->compat_flags & (mac_reg_access[index] >> 2))) { in e1000_mmio_write()
1299 || (s->compat_flags & (mac_reg_access[index] >> 2))) { in e1000_mmio_read()
1356 NetClientState *nc = qemu_get_queue(s->nic); in e1000_pre_save()
1359 * If link is down and auto-negotiation is supported and ongoing, in e1000_pre_save()
1360 * complete auto-negotiation immediately. This allows us to look in e1000_pre_save()
1361 * at MII_BMSR_AN_COMP to infer link status on load. in e1000_pre_save()
1363 if (nc->link_down && have_autoneg(s)) { in e1000_pre_save()
1364 s->phy_reg[MII_BMSR] |= MII_BMSR_AN_COMP; in e1000_pre_save()
1368 if (chkflag(TSO) || !s->use_tso_for_migration) { in e1000_pre_save()
1374 s->mig_props = s->tx.props; in e1000_pre_save()
1379 s->mig_props = s->tx.tso_props; in e1000_pre_save()
1387 NetClientState *nc = qemu_get_queue(s->nic); in e1000_post_load()
1389 s->mit_ide = 0; in e1000_post_load()
1390 s->mit_timer_on = true; in e1000_post_load()
1391 timer_mod(s->mit_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 1); in e1000_post_load()
1394 * to link status bit in mac_reg[STATUS]. in e1000_post_load()
1395 * Alternatively, restart link negotiation if it was in progress. */ in e1000_post_load()
1396 nc->link_down = (s->mac_reg[STATUS] & E1000_STATUS_LU) == 0; in e1000_post_load()
1398 if (have_autoneg(s) && !(s->phy_reg[MII_BMSR] & MII_BMSR_AN_COMP)) { in e1000_post_load()
1399 nc->link_down = false; in e1000_post_load()
1400 timer_mod(s->autoneg_timer, in e1000_post_load()
1404 s->tx.props = s->mig_props; in e1000_post_load()
1405 if (!s->received_tx_tso) { in e1000_post_load()
1410 s->tx.tso_props = s->mig_props; in e1000_post_load()
1418 s->received_tx_tso = true; in e1000_tx_tso_post_load()
1570 * EEPROM contents documented in Tables 5-2 and 5-3, pp. 98-102.
1595 memory_region_init_io(&d->mmio, OBJECT(d), &e1000_mmio_ops, d, in e1000_mmio_setup()
1596 "e1000-mmio", PNPMMIO_SIZE); in e1000_mmio_setup()
1597 memory_region_add_coalescing(&d->mmio, 0, excluded_regs[0]); in e1000_mmio_setup()
1599 memory_region_add_coalescing(&d->mmio, excluded_regs[i] + 4, in e1000_mmio_setup()
1600 excluded_regs[i+1] - excluded_regs[i] - 4); in e1000_mmio_setup()
1601 memory_region_init_io(&d->io, OBJECT(d), &e1000_io_ops, d, "e1000-io", IOPORT_SIZE); in e1000_mmio_setup()
1609 timer_free(d->autoneg_timer); in pci_e1000_uninit()
1610 timer_free(d->mit_timer); in pci_e1000_uninit()
1611 timer_free(d->flush_queue_timer); in pci_e1000_uninit()
1612 qemu_del_nic(d->nic); in pci_e1000_uninit()
1632 (pci_dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) { in e1000_write_config()
1633 qemu_flush_queued_packets(qemu_get_queue(s->nic)); in e1000_write_config()
1644 pci_dev->config_write = e1000_write_config; in pci_e1000_realize()
1646 pci_conf = pci_dev->config; in pci_e1000_realize()
1655 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); in pci_e1000_realize()
1657 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->io); in pci_e1000_realize()
1659 qemu_macaddr_default_if_unset(&d->conf.macaddr); in pci_e1000_realize()
1660 macaddr = d->conf.macaddr.a; in pci_e1000_realize()
1662 e1000x_core_prepare_eeprom(d->eeprom_data, in pci_e1000_realize()
1665 PCI_DEVICE_GET_CLASS(pci_dev)->device_id, in pci_e1000_realize()
1668 d->nic = qemu_new_nic(&net_e1000_info, &d->conf, in pci_e1000_realize()
1669 object_get_typename(OBJECT(d)), dev->id, in pci_e1000_realize()
1670 &dev->mem_reentrancy_guard, d); in pci_e1000_realize()
1672 qemu_format_nic_info_str(qemu_get_queue(d->nic), macaddr); in pci_e1000_realize()
1674 d->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, e1000_autoneg_timer, d); in pci_e1000_realize()
1675 d->mit_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000_mit_timer, d); in pci_e1000_realize()
1676 d->flush_queue_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, in pci_e1000_realize()
1686 DEFINE_PROP_BIT("init-vet", E1000State,
1706 k->realize = pci_e1000_realize; in e1000_class_init()
1707 k->exit = pci_e1000_uninit; in e1000_class_init()
1708 k->romfile = "efi-e1000.rom"; in e1000_class_init()
1709 k->vendor_id = PCI_VENDOR_ID_INTEL; in e1000_class_init()
1710 k->device_id = info->device_id; in e1000_class_init()
1711 k->revision = info->revision; in e1000_class_init()
1712 e->phy_id2 = info->phy_id2; in e1000_class_init()
1713 k->class_id = PCI_CLASS_NETWORK_ETHERNET; in e1000_class_init()
1714 rc->phases.hold = e1000_reset_hold; in e1000_class_init()
1715 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); in e1000_class_init()
1716 dc->desc = "Intel Gigabit Ethernet"; in e1000_class_init()
1717 dc->vmsd = &vmstate_e1000; in e1000_class_init()
1724 device_add_bootindex_property(obj, &n->conf.bootindex, in e1000_instance_init()
1725 "bootindex", "/ethernet-phy@0", in e1000_instance_init()
1750 .name = "e1000-82544gc",
1756 .name = "e1000-82545em",
1772 type_info.name = info->name; in e1000_register_types()