Lines Matching +full:db0 +full:- +full:db7
4 * https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
8 * Written-by: Vikram Garhwal<fnu.vikram@xilinx.com>
41 #include "hw/qdev-properties.h"
46 #include "hw/net/xlnx-zynqmp-can.h"
153 FIELD(TXFIFO_DATA1, DB0, 24, 8)
161 FIELD(TXFIFO_DATA2, DB7, 0, 8)
171 FIELD(TXHPB_DATA1, DB0, 24, 8)
179 FIELD(TXHPB_DATA2, DB7, 0, 8)
190 FIELD(RXFIFO_DATA1, DB0, 24, 8)
198 FIELD(RXFIFO_DATA2, DB7, 0, 8)
258 if ((fifo32_num_free(&s->tx_fifo) / CAN_FRAME_SIZE) > in can_update_irq()
259 ARRAY_FIELD_EX32(s->regs, WIR, EW)) { in can_update_irq()
260 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXFWMEMP, 1); in can_update_irq()
263 if ((fifo32_num_used(&s->rx_fifo) / CAN_FRAME_SIZE) > in can_update_irq()
264 ARRAY_FIELD_EX32(s->regs, WIR, FW)) { in can_update_irq()
265 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFWMFLL, 1); in can_update_irq()
269 if (fifo32_num_used(&s->rx_fifo) >= CAN_FRAME_SIZE) { in can_update_irq()
270 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXNEMP, 1); in can_update_irq()
274 if (fifo32_is_empty(&s->tx_fifo)) { in can_update_irq()
275 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXFEMP, 1); in can_update_irq()
278 if (fifo32_is_full(&s->tx_fifo)) { in can_update_irq()
279 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXFLL, 1); in can_update_irq()
282 if (fifo32_is_full(&s->txhpb_fifo)) { in can_update_irq()
283 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXBFLL, 1); in can_update_irq()
286 irq = s->regs[R_INTERRUPT_STATUS_REGISTER]; in can_update_irq()
287 irq &= s->regs[R_INTERRUPT_ENABLE_REGISTER]; in can_update_irq()
289 trace_xlnx_can_update_irq(s->regs[R_INTERRUPT_STATUS_REGISTER], in can_update_irq()
290 s->regs[R_INTERRUPT_ENABLE_REGISTER], irq); in can_update_irq()
291 qemu_set_irq(s->irq, irq); in can_update_irq()
296 XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque); in can_ier_post_write()
303 XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque); in can_icr_pre_write()
305 s->regs[R_INTERRUPT_STATUS_REGISTER] &= ~val; in can_icr_pre_write()
314 register_reset(&s->reg_info[R_SOFTWARE_RESET_REGISTER]); in can_config_reset()
315 register_reset(&s->reg_info[R_MODE_SELECT_REGISTER]); in can_config_reset()
317 &s->reg_info[R_ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER]); in can_config_reset()
318 register_reset(&s->reg_info[R_ARBITRATION_PHASE_BIT_TIMING_REGISTER]); in can_config_reset()
319 register_reset(&s->reg_info[R_STATUS_REGISTER]); in can_config_reset()
320 register_reset(&s->reg_info[R_INTERRUPT_STATUS_REGISTER]); in can_config_reset()
321 register_reset(&s->reg_info[R_INTERRUPT_ENABLE_REGISTER]); in can_config_reset()
322 register_reset(&s->reg_info[R_INTERRUPT_CLEAR_REGISTER]); in can_config_reset()
323 register_reset(&s->reg_info[R_WIR]); in can_config_reset()
328 register_reset(&s->reg_info[R_ERROR_COUNTER_REGISTER]); in can_config_mode()
329 register_reset(&s->reg_info[R_ERROR_STATUS_REGISTER]); in can_config_mode()
332 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, CONFIG, 1); in can_config_mode()
333 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, WKUP, 0); in can_config_mode()
334 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, SLP, 0); in can_config_mode()
335 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, BSOFF, 0); in can_config_mode()
336 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, ERROR, 0); in can_config_mode()
337 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOFLW, 0); in can_config_mode()
338 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 0); in can_config_mode()
339 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXOK, 0); in can_config_mode()
340 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, ARBLST, 0); in can_config_mode()
347 bool sleep_status = ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP); in update_status_register_mode_bits()
348 bool sleep_mode = ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SLEEP); in update_status_register_mode_bits()
355 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, LBACK, 0); in update_status_register_mode_bits()
356 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SLEEP, 0); in update_status_register_mode_bits()
357 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SNOOP, 0); in update_status_register_mode_bits()
358 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, NORMAL, 0); in update_status_register_mode_bits()
361 if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, LBACK)) { in update_status_register_mode_bits()
362 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, LBACK, 1); in update_status_register_mode_bits()
363 } else if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SLEEP)) { in update_status_register_mode_bits()
364 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SLEEP, 1); in update_status_register_mode_bits()
365 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, SLP, in update_status_register_mode_bits()
367 } else if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SNOOP)) { in update_status_register_mode_bits()
368 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SNOOP, 1); in update_status_register_mode_bits()
373 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, NORMAL, 1); in update_status_register_mode_bits()
375 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, WKUP, in update_status_register_mode_bits()
384 ARRAY_FIELD_DP32(s->regs, MODE_SELECT_REGISTER, SLEEP, 0); in can_exit_sleep_mode()
390 frame->can_id = data[0]; in generate_frame()
391 frame->can_dlc = FIELD_EX32(data[1], TXFIFO_DLC, DLC); in generate_frame()
393 frame->data[0] = FIELD_EX32(data[2], TXFIFO_DATA1, DB3); in generate_frame()
394 frame->data[1] = FIELD_EX32(data[2], TXFIFO_DATA1, DB2); in generate_frame()
395 frame->data[2] = FIELD_EX32(data[2], TXFIFO_DATA1, DB1); in generate_frame()
396 frame->data[3] = FIELD_EX32(data[2], TXFIFO_DATA1, DB0); in generate_frame()
398 frame->data[4] = FIELD_EX32(data[3], TXFIFO_DATA2, DB7); in generate_frame()
399 frame->data[5] = FIELD_EX32(data[3], TXFIFO_DATA2, DB6); in generate_frame()
400 frame->data[6] = FIELD_EX32(data[3], TXFIFO_DATA2, DB5); in generate_frame()
401 frame->data[7] = FIELD_EX32(data[3], TXFIFO_DATA2, DB4); in generate_frame()
406 if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, SRST)) { in tx_ready_check()
415 if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) { in tx_ready_check()
425 if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SNOOP)) { in tx_ready_check()
440 bool is_txhpb = fifo == &s->txhpb_fifo; in read_tx_frame()
459 data[0] = s->regs[is_txhpb ? R_TXHPB_ID : R_TXFIFO_ID]; in read_tx_frame()
464 data[1] = s->regs[is_txhpb ? R_TXHPB_DLC : R_TXFIFO_DLC]; in read_tx_frame()
469 data[2] = s->regs[is_txhpb ? R_TXHPB_DATA1 : R_TXFIFO_DATA1]; in read_tx_frame()
502 if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, LBACK)) { in transfer_fifo()
510 if (fifo32_is_full(&s->rx_fifo)) { in transfer_fifo()
511 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOFLW, 1); in transfer_fifo()
514 fifo32_push(&s->rx_fifo, data[i]); in transfer_fifo()
517 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1); in transfer_fifo()
528 can_bus_client_send(&s->bus_client, &frame, 1); in transfer_fifo()
532 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXOK, 1); in transfer_fifo()
533 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, TXBFLL, 0); in transfer_fifo()
535 if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP)) { in transfer_fifo()
544 XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque); in can_srr_pre_write()
546 ARRAY_FIELD_DP32(s->regs, SOFTWARE_RESET_REGISTER, CEN, in can_srr_pre_write()
556 if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) { in can_srr_pre_write()
564 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, CONFIG, 0); in can_srr_pre_write()
566 ptimer_transaction_begin(s->can_timer); in can_srr_pre_write()
567 ptimer_set_count(s->can_timer, 0); in can_srr_pre_write()
568 ptimer_transaction_commit(s->can_timer); in can_srr_pre_write()
571 transfer_fifo(s, &s->txhpb_fifo); in can_srr_pre_write()
572 transfer_fifo(s, &s->tx_fifo); in can_srr_pre_write()
577 return s->regs[R_SOFTWARE_RESET_REGISTER]; in can_srr_pre_write()
582 XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque); in can_msr_pre_write()
602 if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) { in can_msr_pre_write()
604 s->regs[R_MODE_SELECT_REGISTER] = val; in can_msr_pre_write()
608 ARRAY_FIELD_DP32(s->regs, MODE_SELECT_REGISTER, SLEEP, sleep_mode_bit); in can_msr_pre_write()
627 return s->regs[R_MODE_SELECT_REGISTER]; in can_msr_pre_write()
632 XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque); in can_brpr_pre_write()
635 if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) { in can_brpr_pre_write()
636 return s->regs[R_ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER]; in can_brpr_pre_write()
644 XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque); in can_btr_pre_write()
647 if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) { in can_btr_pre_write()
648 return s->regs[R_ARBITRATION_PHASE_BIT_TIMING_REGISTER]; in can_btr_pre_write()
656 XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque); in can_tcr_pre_write()
659 ptimer_transaction_begin(s->can_timer); in can_tcr_pre_write()
660 ptimer_set_count(s->can_timer, 0); in can_tcr_pre_write()
661 ptimer_transaction_commit(s->can_timer); in can_tcr_pre_write()
673 if (!((ARRAY_FIELD_EX32(s->regs, AFR, UAF1)) | in update_rx_fifo()
674 (ARRAY_FIELD_EX32(s->regs, AFR, UAF2)) | in update_rx_fifo()
675 (ARRAY_FIELD_EX32(s->regs, AFR, UAF3)) | in update_rx_fifo()
676 (ARRAY_FIELD_EX32(s->regs, AFR, UAF4)))) { in update_rx_fifo()
684 if (ARRAY_FIELD_EX32(s->regs, AFR, UAF1)) { in update_rx_fifo()
685 uint32_t id_masked = s->regs[R_AFMR1] & frame->can_id; in update_rx_fifo()
686 uint32_t filter_id_masked = s->regs[R_AFMR1] & s->regs[R_AFIR1]; in update_rx_fifo()
693 if (ARRAY_FIELD_EX32(s->regs, AFR, UAF2)) { in update_rx_fifo()
694 uint32_t id_masked = s->regs[R_AFMR2] & frame->can_id; in update_rx_fifo()
695 uint32_t filter_id_masked = s->regs[R_AFMR2] & s->regs[R_AFIR2]; in update_rx_fifo()
702 if (ARRAY_FIELD_EX32(s->regs, AFR, UAF3)) { in update_rx_fifo()
703 uint32_t id_masked = s->regs[R_AFMR3] & frame->can_id; in update_rx_fifo()
704 uint32_t filter_id_masked = s->regs[R_AFMR3] & s->regs[R_AFIR3]; in update_rx_fifo()
711 if (ARRAY_FIELD_EX32(s->regs, AFR, UAF4)) { in update_rx_fifo()
712 uint32_t id_masked = s->regs[R_AFMR4] & frame->can_id; in update_rx_fifo()
713 uint32_t filter_id_masked = s->regs[R_AFMR4] & s->regs[R_AFIR4]; in update_rx_fifo()
721 trace_xlnx_can_rx_fifo_filter_reject(frame->can_id, frame->can_dlc); in update_rx_fifo()
726 if (filter_pass && frame->can_dlc <= MAX_DLC) { in update_rx_fifo()
728 if (fifo32_is_full(&s->rx_fifo)) { in update_rx_fifo()
729 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOFLW, 1); in update_rx_fifo()
731 timestamp = CAN_TIMER_MAX - ptimer_get_count(s->can_timer); in update_rx_fifo()
733 fifo32_push(&s->rx_fifo, frame->can_id); in update_rx_fifo()
735 fifo32_push(&s->rx_fifo, deposit32(0, R_RXFIFO_DLC_DLC_SHIFT, in update_rx_fifo()
737 frame->can_dlc) | in update_rx_fifo()
743 fifo32_push(&s->rx_fifo, deposit32(0, R_RXFIFO_DATA1_DB3_SHIFT, in update_rx_fifo()
745 frame->data[0]) | in update_rx_fifo()
748 frame->data[1]) | in update_rx_fifo()
751 frame->data[2]) | in update_rx_fifo()
754 frame->data[3])); in update_rx_fifo()
756 fifo32_push(&s->rx_fifo, deposit32(0, R_RXFIFO_DATA2_DB7_SHIFT, in update_rx_fifo()
758 frame->data[4]) | in update_rx_fifo()
761 frame->data[5]) | in update_rx_fifo()
764 frame->data[6]) | in update_rx_fifo()
767 frame->data[7])); in update_rx_fifo()
769 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1); in update_rx_fifo()
770 trace_xlnx_can_rx_data(frame->can_id, frame->can_dlc, in update_rx_fifo()
771 frame->data[0], frame->data[1], in update_rx_fifo()
772 frame->data[2], frame->data[3], in update_rx_fifo()
773 frame->data[4], frame->data[5], in update_rx_fifo()
774 frame->data[6], frame->data[7]); in update_rx_fifo()
783 XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque); in can_rxfifo_post_read_id()
784 unsigned used = fifo32_num_used(&s->rx_fifo); in can_rxfifo_post_read_id()
787 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXUFLW, 1); in can_rxfifo_post_read_id()
789 val = s->regs[R_RXFIFO_ID] = fifo32_pop(&s->rx_fifo); in can_rxfifo_post_read_id()
790 s->regs[R_RXFIFO_DLC] = fifo32_pop(&s->rx_fifo); in can_rxfifo_post_read_id()
791 s->regs[R_RXFIFO_DATA1] = fifo32_pop(&s->rx_fifo); in can_rxfifo_post_read_id()
792 s->regs[R_RXFIFO_DATA2] = fifo32_pop(&s->rx_fifo); in can_rxfifo_post_read_id()
801 XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque); in can_filter_enable_post_write()
803 if (ARRAY_FIELD_EX32(s->regs, AFR, UAF1) && in can_filter_enable_post_write()
804 ARRAY_FIELD_EX32(s->regs, AFR, UAF2) && in can_filter_enable_post_write()
805 ARRAY_FIELD_EX32(s->regs, AFR, UAF3) && in can_filter_enable_post_write()
806 ARRAY_FIELD_EX32(s->regs, AFR, UAF4)) { in can_filter_enable_post_write()
807 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, ACFBSY, 1); in can_filter_enable_post_write()
809 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, ACFBSY, 0); in can_filter_enable_post_write()
815 XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque); in can_filter_mask_pre_write()
816 uint32_t reg_idx = (reg->access->addr) / 4; in can_filter_mask_pre_write()
817 uint32_t filter_number = (reg_idx - R_AFMR1) / 2; in can_filter_mask_pre_write()
820 if (!(s->regs[R_AFR] & (1 << filter_number))) { in can_filter_mask_pre_write()
821 s->regs[reg_idx] = val; in can_filter_mask_pre_write()
823 trace_xlnx_can_filter_mask_pre_write(filter_number, s->regs[reg_idx]); in can_filter_mask_pre_write()
832 return s->regs[reg_idx]; in can_filter_mask_pre_write()
837 XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque); in can_filter_id_pre_write()
838 uint32_t reg_idx = (reg->access->addr) / 4; in can_filter_id_pre_write()
839 uint32_t filter_number = (reg_idx - R_AFIR1) / 2; in can_filter_id_pre_write()
841 if (!(s->regs[R_AFR] & (1 << filter_number))) { in can_filter_id_pre_write()
842 s->regs[reg_idx] = val; in can_filter_id_pre_write()
844 trace_xlnx_can_filter_id_pre_write(filter_number, s->regs[reg_idx]); in can_filter_id_pre_write()
853 return s->regs[reg_idx]; in can_filter_id_pre_write()
858 XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque); in can_tx_post_write()
860 bool is_txhpb = reg->access->addr > A_TXFIFO_DATA2; in can_tx_post_write()
862 bool initiate_transfer = (reg->access->addr == A_TXFIFO_DATA2) || in can_tx_post_write()
863 (reg->access->addr == A_TXHPB_DATA2); in can_tx_post_write()
865 Fifo32 *f = is_txhpb ? &s->txhpb_fifo : &s->tx_fifo; in can_tx_post_write()
877 ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) { in can_tx_post_write()
1000 for (i = R_RXFIFO_ID; i < ARRAY_SIZE(s->reg_info); ++i) { in xlnx_zynqmp_can_reset_init()
1001 register_reset(&s->reg_info[i]); in xlnx_zynqmp_can_reset_init()
1004 ptimer_transaction_begin(s->can_timer); in xlnx_zynqmp_can_reset_init()
1005 ptimer_set_count(s->can_timer, 0); in xlnx_zynqmp_can_reset_init()
1006 ptimer_transaction_commit(s->can_timer); in xlnx_zynqmp_can_reset_init()
1015 register_reset(&s->reg_info[i]); in xlnx_zynqmp_can_reset_hold()
1024 fifo32_reset(&s->rx_fifo); in xlnx_zynqmp_can_reset_hold()
1025 fifo32_reset(&s->tx_fifo); in xlnx_zynqmp_can_reset_hold()
1026 fifo32_reset(&s->txhpb_fifo); in xlnx_zynqmp_can_reset_hold()
1034 if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, SRST)) { in xlnx_zynqmp_can_can_receive()
1042 if ((ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) == 0) { in xlnx_zynqmp_can_can_receive()
1067 if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SNOOP)) { in xlnx_zynqmp_can_receive()
1070 } else if ((ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP))) { in xlnx_zynqmp_can_receive()
1077 } else if ((ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP)) == 0) { in xlnx_zynqmp_can_receive()
1084 trace_xlnx_can_rx_discard(s->regs[R_STATUS_REGISTER]); in xlnx_zynqmp_can_receive()
1098 s->bus_client.info = &can_xilinx_bus_client_info; in xlnx_zynqmp_can_connect_to_bus()
1100 if (can_bus_insert_client(bus, &s->bus_client) < 0) { in xlnx_zynqmp_can_connect_to_bus()
1101 return -1; in xlnx_zynqmp_can_connect_to_bus()
1110 if (s->canbus) { in xlnx_zynqmp_can_realize()
1111 if (xlnx_zynqmp_can_connect_to_bus(s, s->canbus) < 0) { in xlnx_zynqmp_can_realize()
1121 fifo32_create(&s->rx_fifo, RXFIFO_SIZE); in xlnx_zynqmp_can_realize()
1122 fifo32_create(&s->tx_fifo, RXFIFO_SIZE); in xlnx_zynqmp_can_realize()
1123 fifo32_create(&s->txhpb_fifo, CAN_FRAME_SIZE); in xlnx_zynqmp_can_realize()
1126 s->can_timer = ptimer_init(xlnx_zynqmp_can_ptimer_cb, s, in xlnx_zynqmp_can_realize()
1129 ptimer_transaction_begin(s->can_timer); in xlnx_zynqmp_can_realize()
1131 ptimer_set_freq(s->can_timer, s->cfg.ext_clk_freq); in xlnx_zynqmp_can_realize()
1132 ptimer_set_limit(s->can_timer, CAN_TIMER_MAX, 1); in xlnx_zynqmp_can_realize()
1133 ptimer_run(s->can_timer, 0); in xlnx_zynqmp_can_realize()
1134 ptimer_transaction_commit(s->can_timer); in xlnx_zynqmp_can_realize()
1144 memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_CAN, in xlnx_zynqmp_can_init()
1148 s->reg_info, s->regs, in xlnx_zynqmp_can_init()
1153 memory_region_add_subregion(&s->iomem, 0x00, ®_array->mem); in xlnx_zynqmp_can_init()
1154 sysbus_init_mmio(sbd, &s->iomem); in xlnx_zynqmp_can_init()
1155 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); in xlnx_zynqmp_can_init()
1185 rc->phases.enter = xlnx_zynqmp_can_reset_init; in xlnx_zynqmp_can_class_init()
1186 rc->phases.hold = xlnx_zynqmp_can_reset_hold; in xlnx_zynqmp_can_class_init()
1187 dc->realize = xlnx_zynqmp_can_realize; in xlnx_zynqmp_can_class_init()
1189 dc->vmsd = &vmstate_can; in xlnx_zynqmp_can_class_init()