Lines Matching +full:revision +full:- +full:id2
30 #include "hw/qdev-properties.h"
221 REG32(TIDMATCH2, 0xac) /* Type ID2 Match reg */
230 REG32(TXCNT, 0x108) /* Error-free Frames transmitted */
231 REG32(TXBCNT, 0x10c) /* Error-free Broadcast Frames */
232 REG32(TXMCNT, 0x110) /* Error-free Multicast Frame */
234 REG32(TX64CNT, 0x118) /* Error-free 64 TX */
235 REG32(TX65CNT, 0x11c) /* Error-free 65-127 TX */
236 REG32(TX128CNT, 0x120) /* Error-free 128-255 TX */
237 REG32(TX256CNT, 0x124) /* Error-free 256-511 */
238 REG32(TX512CNT, 0x128) /* Error-free 512-1023 TX */
239 REG32(TX1024CNT, 0x12c) /* Error-free 1024-1518 TX */
240 REG32(TX1519CNT, 0x130) /* Error-free larger than 1519 TX */
250 REG32(RXCNT, 0x158) /* Error-free Frames Received */
251 REG32(RXBROADCNT, 0x15c) /* Error-free Broadcast Frames RX */
252 REG32(RXMULTICNT, 0x160) /* Error-free Multicast Frames RX */
254 REG32(RX64CNT, 0x168) /* Error-free 64 byte Frames RX */
255 REG32(RX65CNT, 0x16c) /* Error-free 65-127B Frames RX */
256 REG32(RX128CNT, 0x170) /* Error-free 128-255B Frames RX */
257 REG32(RX256CNT, 0x174) /* Error-free 256-512B Frames RX */
258 REG32(RX512CNT, 0x178) /* Error-free 512-1023B Frames RX */
259 REG32(RX1024CNT, 0x17c) /* Error-free 1024-1518B Frames RX */
260 REG32(RX1519CNT, 0x180) /* Error-free 1519-max Frames RX */
394 #define GEM_RX_REJECT (-1)
395 #define GEM_RX_PROMISCUOUS_ACCEPT (-2)
396 #define GEM_RX_BROADCAST_ACCEPT (-3)
397 #define GEM_RX_MULTICAST_HASH_ACCEPT (-4)
398 #define GEM_RX_UNICAST_HASH_ACCEPT (-5)
429 if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { in tx_desc_get_buffer()
474 if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { in rx_desc_get_buffer()
484 if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { in gem_get_desc_len()
487 if (s->regs[R_DMACFG] & (rx_n_tx ? R_DMACFG_RX_BD_EXT_MODE_EN_MASK in gem_get_desc_len()
560 if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, JUMBO_FRAMES)) { in gem_get_max_buf_len()
561 size = s->regs[R_JUMBO_MAX_LEN]; in gem_get_max_buf_len()
562 if (size > s->jumbo_max_len) { in gem_get_max_buf_len()
563 size = s->jumbo_max_len; in gem_get_max_buf_len()
565 " greater than 0x%" PRIx32 "\n", s->jumbo_max_len); in gem_get_max_buf_len()
570 size = FIELD_EX32(s->regs[R_NWCFG], in gem_get_max_buf_len()
579 s->regs[R_ISR] |= flag & ~(s->regs[R_IMR]); in gem_set_isr()
581 s->regs[R_INT_Q1_STATUS + q - 1] |= flag & in gem_set_isr()
582 ~(s->regs[R_INT_Q1_MASK + q - 1]); in gem_set_isr()
595 memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); in gem_init_register_masks()
596 s->regs_ro[R_NWCTRL] = 0xFFF80000; in gem_init_register_masks()
597 s->regs_ro[R_NWSTATUS] = 0xFFFFFFFF; in gem_init_register_masks()
598 s->regs_ro[R_DMACFG] = 0x8E00F000; in gem_init_register_masks()
599 s->regs_ro[R_TXSTATUS] = 0xFFFFFE08; in gem_init_register_masks()
600 s->regs_ro[R_RXQBASE] = 0x00000003; in gem_init_register_masks()
601 s->regs_ro[R_TXQBASE] = 0x00000003; in gem_init_register_masks()
602 s->regs_ro[R_RXSTATUS] = 0xFFFFFFF0; in gem_init_register_masks()
603 s->regs_ro[R_ISR] = 0xFFFFFFFF; in gem_init_register_masks()
604 s->regs_ro[R_IMR] = 0xFFFFFFFF; in gem_init_register_masks()
605 s->regs_ro[R_MODID] = 0xFFFFFFFF; in gem_init_register_masks()
606 for (i = 0; i < s->num_priority_queues; i++) { in gem_init_register_masks()
607 s->regs_ro[R_INT_Q1_STATUS + i] = 0xFFFFFFFF; in gem_init_register_masks()
608 s->regs_ro[R_INT_Q1_ENABLE + i] = 0xFFFFF319; in gem_init_register_masks()
609 s->regs_ro[R_INT_Q1_DISABLE + i] = 0xFFFFF319; in gem_init_register_masks()
610 s->regs_ro[R_INT_Q1_MASK + i] = 0xFFFFFFFF; in gem_init_register_masks()
614 memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc)); in gem_init_register_masks()
615 s->regs_rtc[R_ISR] = 0xFFFFFFFF; in gem_init_register_masks()
616 for (i = 0; i < s->num_priority_queues; i++) { in gem_init_register_masks()
617 s->regs_rtc[R_INT_Q1_STATUS + i] = 0x00000CE6; in gem_init_register_masks()
621 memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c)); in gem_init_register_masks()
622 s->regs_w1c[R_TXSTATUS] = 0x000001F7; in gem_init_register_masks()
623 s->regs_w1c[R_RXSTATUS] = 0x0000000F; in gem_init_register_masks()
626 memset(&s->regs_wo[0], 0, sizeof(s->regs_wo)); in gem_init_register_masks()
627 s->regs_wo[R_NWCTRL] = 0x00073E60; in gem_init_register_masks()
628 s->regs_wo[R_IER] = 0x07FFFFFF; in gem_init_register_masks()
629 s->regs_wo[R_IDR] = 0x07FFFFFF; in gem_init_register_masks()
630 for (i = 0; i < s->num_priority_queues; i++) { in gem_init_register_masks()
631 s->regs_wo[R_INT_Q1_ENABLE + i] = 0x00000CE6; in gem_init_register_masks()
632 s->regs_wo[R_INT_Q1_DISABLE + i] = 0x00000CE6; in gem_init_register_masks()
642 DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down); in phy_update_link()
645 if (qemu_get_queue(s->nic)->link_down) { in phy_update_link()
646 s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL | in phy_update_link()
648 s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC; in phy_update_link()
650 s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL | in phy_update_link()
652 s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC | in phy_update_link()
666 if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_RECEIVE)) { in gem_can_receive()
667 if (s->can_rx_state != 1) { in gem_can_receive()
668 s->can_rx_state = 1; in gem_can_receive()
669 DB_PRINT("can't receive - no enable\n"); in gem_can_receive()
674 for (i = 0; i < s->num_priority_queues; i++) { in gem_can_receive()
675 if (rx_desc_get_ownership(s->rx_desc[i]) != 1) { in gem_can_receive()
680 if (i == s->num_priority_queues) { in gem_can_receive()
681 if (s->can_rx_state != 2) { in gem_can_receive()
682 s->can_rx_state = 2; in gem_can_receive()
683 DB_PRINT("can't receive - all the buffer descriptors are busy\n"); in gem_can_receive()
688 if (s->can_rx_state != 0) { in gem_can_receive()
689 s->can_rx_state = 0; in gem_can_receive()
703 qemu_set_irq(s->irq[0], !!s->regs[R_ISR]); in gem_update_int_status()
705 for (i = 1; i < s->num_priority_queues; ++i) { in gem_update_int_status()
706 qemu_set_irq(s->irq[i], !!s->regs[R_INT_Q1_STATUS + i - 1]); in gem_update_int_status()
720 octets = ((uint64_t)(s->regs[R_OCTRXLO]) << 32) | in gem_receive_updatestats()
721 s->regs[R_OCTRXHI]; in gem_receive_updatestats()
723 s->regs[R_OCTRXLO] = octets >> 32; in gem_receive_updatestats()
724 s->regs[R_OCTRXHI] = octets; in gem_receive_updatestats()
726 /* Error-free Frames received */ in gem_receive_updatestats()
727 s->regs[R_RXCNT]++; in gem_receive_updatestats()
729 /* Error-free Broadcast Frames counter */ in gem_receive_updatestats()
731 s->regs[R_RXBROADCNT]++; in gem_receive_updatestats()
734 /* Error-free Multicast Frames counter */ in gem_receive_updatestats()
736 s->regs[R_RXMULTICNT]++; in gem_receive_updatestats()
740 s->regs[R_RX64CNT]++; in gem_receive_updatestats()
742 s->regs[R_RX65CNT]++; in gem_receive_updatestats()
744 s->regs[R_RX128CNT]++; in gem_receive_updatestats()
746 s->regs[R_RX256CNT]++; in gem_receive_updatestats()
748 s->regs[R_RX512CNT]++; in gem_receive_updatestats()
750 s->regs[R_RX1024CNT]++; in gem_receive_updatestats()
752 s->regs[R_RX1519CNT]++; in gem_receive_updatestats()
780 for (index_bit = 5; index_bit >= 0; index_bit--) { in calc_mac_hash()
789 mac_bit--; in calc_mac_hash()
811 if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, PROMISC)) { in gem_mac_address_filter()
817 if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, NO_BROADCAST)) { in gem_mac_address_filter()
823 /* Accept packets -w- hash match? */ in gem_mac_address_filter()
825 if ((is_mc && (FIELD_EX32(s->regs[R_NWCFG], NWCFG, MULTICAST_HASH_EN))) || in gem_mac_address_filter()
826 (!is_mc && FIELD_EX32(s->regs[R_NWCFG], NWCFG, UNICAST_HASH_EN))) { in gem_mac_address_filter()
831 buckets = ((uint64_t)s->regs[R_HASHHI] << 32) | s->regs[R_HASHLO]; in gem_mac_address_filter()
839 gem_spaddr = (uint8_t *)&(s->regs[R_SPADDR1LO]); in gem_mac_address_filter()
840 for (i = 3; i >= 0; i--) { in gem_mac_address_filter()
841 if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) { in gem_mac_address_filter()
858 for (i = 0; i < s->num_type1_screeners; i++) { in get_queue_from_screen()
859 reg = s->regs[R_SCREENING_TYPE1_REG0 + i]; in get_queue_from_screen()
888 for (i = 0; i < s->num_type2_screeners; i++) { in get_queue_from_screen()
889 reg = s->regs[R_SCREENING_TYPE2_REG0 + i]; in get_queue_from_screen()
898 if (et_idx > s->num_type2_screeners) { in get_queue_from_screen()
902 if (type == s->regs[R_SCREENING_TYPE2_ETHERTYPE_REG0 + in get_queue_from_screen()
923 if (cr_idx > s->num_type2_screeners) { in get_queue_from_screen()
928 cr0 = s->regs[R_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2]; in get_queue_from_screen()
929 cr1 = s->regs[R_TYPE2_COMPARE_0_WORD_1 + cr_idx * 2]; in get_queue_from_screen()
935 "unimplemented - assuming UDP\n"); in get_queue_from_screen()
957 * all-ones so we compare all 32 bits. in get_queue_from_screen()
991 base_addr = s->regs[tx ? R_TXQBASE : R_RXQBASE]; in gem_get_queue_base_addr()
993 case 1 ... (MAX_PRIORITY_QUEUES - 1): in gem_get_queue_base_addr()
994 base_addr = s->regs[(tx ? R_TRANSMIT_Q1_PTR : in gem_get_queue_base_addr()
995 R_RECEIVE_Q1_PTR) + q - 1]; in gem_get_queue_base_addr()
1018 if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { in gem_get_desc_addr()
1019 desc_addr = s->regs[tx ? R_TBQPH : R_RBQPH]; in gem_get_desc_addr()
1022 desc_addr |= tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q]; in gem_get_desc_addr()
1043 address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, in gem_get_rx_desc()
1044 s->rx_desc[q], in gem_get_rx_desc()
1048 if (rx_desc_get_ownership(s->rx_desc[q]) == 1) { in gem_get_rx_desc()
1050 s->regs[R_RXSTATUS] |= R_RXSTATUS_BUF_NOT_AVAILABLE_MASK; in gem_get_rx_desc()
1078 if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, LEN_ERR_DISCARD)) { in gem_receive()
1087 return -1; in gem_receive()
1095 rxbuf_offset = FIELD_EX32(s->regs[R_NWCFG], NWCFG, RECV_BUF_OFFSET); in gem_receive()
1100 rxbufsize = FIELD_EX32(s->regs[R_DMACFG], DMACFG, RX_BUF_SIZE); in gem_receive()
1121 if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, FCS_REMOVE)) { in gem_receive()
1126 if (size > MAX_FRAME_SIZE - sizeof(crc_val)) { in gem_receive()
1127 size = MAX_FRAME_SIZE - sizeof(crc_val); in gem_receive()
1134 memcpy(s->rx_packet, buf, size); in gem_receive()
1135 memset(s->rx_packet + size, 0, MAX_FRAME_SIZE - size); in gem_receive()
1136 rxbuf_ptr = s->rx_packet; in gem_receive()
1137 crc_val = cpu_to_le32(crc32(0, s->rx_packet, MAX(size, 60))); in gem_receive()
1138 memcpy(s->rx_packet + size, &crc_val, sizeof(crc_val)); in gem_receive()
1152 return -1; in gem_receive()
1160 return -1; in gem_receive()
1165 rx_desc_get_buffer(s, s->rx_desc[q])); in gem_receive()
1168 address_space_write(&s->dma_as, rx_desc_get_buffer(s, s->rx_desc[q]) + in gem_receive()
1173 bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); in gem_receive()
1175 rx_desc_clear_control(s->rx_desc[q]); in gem_receive()
1179 rx_desc_set_sof(s->rx_desc[q]); in gem_receive()
1183 rx_desc_set_eof(s->rx_desc[q]); in gem_receive()
1184 rx_desc_set_length(s->rx_desc[q], size); in gem_receive()
1186 rx_desc_set_ownership(s->rx_desc[q]); in gem_receive()
1192 rx_desc_set_broadcast(s->rx_desc[q]); in gem_receive()
1195 rx_desc_set_unicast_hash(s->rx_desc[q]); in gem_receive()
1198 rx_desc_set_multicast_hash(s->rx_desc[q]); in gem_receive()
1203 rx_desc_set_sar(s->rx_desc[q], maf); in gem_receive()
1206 /* Descriptor write-back. */ in gem_receive()
1208 address_space_write(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, in gem_receive()
1209 s->rx_desc[q], in gem_receive()
1213 if (rx_desc_get_wrap(s->rx_desc[q])) { in gem_receive()
1215 s->rx_desc_addr[q] = gem_get_rx_queue_base_addr(s, q); in gem_receive()
1218 s->rx_desc_addr[q] += 4 * gem_get_desc_len(s, true); in gem_receive()
1227 s->regs[R_RXSTATUS] |= R_RXSTATUS_FRAME_RECEIVED_MASK; in gem_receive()
1246 octets = ((uint64_t)(s->regs[R_OCTTXLO]) << 32) | in gem_transmit_updatestats()
1247 s->regs[R_OCTTXHI]; in gem_transmit_updatestats()
1249 s->regs[R_OCTTXLO] = octets >> 32; in gem_transmit_updatestats()
1250 s->regs[R_OCTTXHI] = octets; in gem_transmit_updatestats()
1252 /* Error-free Frames transmitted */ in gem_transmit_updatestats()
1253 s->regs[R_TXCNT]++; in gem_transmit_updatestats()
1255 /* Error-free Broadcast Frames counter */ in gem_transmit_updatestats()
1257 s->regs[R_TXBCNT]++; in gem_transmit_updatestats()
1260 /* Error-free Multicast Frames counter */ in gem_transmit_updatestats()
1262 s->regs[R_TXMCNT]++; in gem_transmit_updatestats()
1266 s->regs[R_TX64CNT]++; in gem_transmit_updatestats()
1268 s->regs[R_TX65CNT]++; in gem_transmit_updatestats()
1270 s->regs[R_TX128CNT]++; in gem_transmit_updatestats()
1272 s->regs[R_TX256CNT]++; in gem_transmit_updatestats()
1274 s->regs[R_TX512CNT]++; in gem_transmit_updatestats()
1276 s->regs[R_TX1024CNT]++; in gem_transmit_updatestats()
1278 s->regs[R_TX1519CNT]++; in gem_transmit_updatestats()
1295 if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_TRANSMIT)) { in gem_transmit()
1305 p = s->tx_packet; in gem_transmit()
1308 for (q = s->num_priority_queues - 1; q >= 0; q--) { in gem_transmit()
1313 address_space_read(&s->dma_as, packet_desc_addr, in gem_transmit()
1320 if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_TRANSMIT)) { in gem_transmit()
1335 if (tx_desc_get_length(desc) > gem_get_max_buf_len(s, true) - in gem_transmit()
1336 (p - s->tx_packet)) { in gem_transmit()
1340 gem_get_max_buf_len(s, true) - (p - s->tx_packet)); in gem_transmit()
1348 address_space_read(&s->dma_as, tx_desc_get_buffer(s, desc), in gem_transmit()
1362 address_space_read(&s->dma_as, desc_addr, in gem_transmit()
1366 address_space_write(&s->dma_as, desc_addr, in gem_transmit()
1371 s->tx_desc_addr[q] = gem_get_tx_queue_base_addr(s, q); in gem_transmit()
1373 s->tx_desc_addr[q] = packet_desc_addr + in gem_transmit()
1376 DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]); in gem_transmit()
1378 s->regs[R_TXSTATUS] |= R_TXSTATUS_TRANSMIT_COMPLETE_MASK; in gem_transmit()
1385 if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, TX_PBUF_CSUM_OFFLOAD)) { in gem_transmit()
1386 net_checksum_calculate(s->tx_packet, total_bytes, CSUM_ALL); in gem_transmit()
1390 gem_transmit_updatestats(s, s->tx_packet, total_bytes); in gem_transmit()
1393 if (s->phy_loop || FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, in gem_transmit()
1395 qemu_receive_packet(qemu_get_queue(s->nic), s->tx_packet, in gem_transmit()
1398 qemu_send_packet(qemu_get_queue(s->nic), s->tx_packet, in gem_transmit()
1403 p = s->tx_packet; in gem_transmit()
1409 if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { in gem_transmit()
1410 packet_desc_addr = s->regs[R_TBQPH]; in gem_transmit()
1420 address_space_read(&s->dma_as, packet_desc_addr, in gem_transmit()
1426 s->regs[R_TXSTATUS] |= R_TXSTATUS_USED_BIT_READ_MASK; in gem_transmit()
1438 memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); in gem_phy_reset()
1439 s->phy_regs[PHY_REG_CONTROL] = 0x1140; in gem_phy_reset()
1440 s->phy_regs[PHY_REG_STATUS] = 0x7969; in gem_phy_reset()
1441 s->phy_regs[PHY_REG_PHYID1] = 0x0141; in gem_phy_reset()
1442 s->phy_regs[PHY_REG_PHYID2] = 0x0CC2; in gem_phy_reset()
1443 s->phy_regs[PHY_REG_ANEGADV] = 0x01E1; in gem_phy_reset()
1444 s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1; in gem_phy_reset()
1445 s->phy_regs[PHY_REG_ANEGEXP] = 0x000F; in gem_phy_reset()
1446 s->phy_regs[PHY_REG_NEXTP] = 0x2001; in gem_phy_reset()
1447 s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6; in gem_phy_reset()
1448 s->phy_regs[PHY_REG_100BTCTRL] = 0x0300; in gem_phy_reset()
1449 s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00; in gem_phy_reset()
1450 s->phy_regs[PHY_REG_EXTSTAT] = 0x3000; in gem_phy_reset()
1451 s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078; in gem_phy_reset()
1452 s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00; in gem_phy_reset()
1453 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60; in gem_phy_reset()
1454 s->phy_regs[PHY_REG_LED] = 0x4100; in gem_phy_reset()
1455 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A; in gem_phy_reset()
1456 s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B; in gem_phy_reset()
1471 memset(&s->regs[0], 0, sizeof(s->regs)); in gem_reset()
1472 s->regs[R_NWCFG] = 0x00080000; in gem_reset()
1473 s->regs[R_NWSTATUS] = 0x00000006; in gem_reset()
1474 s->regs[R_DMACFG] = 0x00020784; in gem_reset()
1475 s->regs[R_IMR] = 0x07ffffff; in gem_reset()
1476 s->regs[R_TXPAUSE] = 0x0000ffff; in gem_reset()
1477 s->regs[R_TXPARTIALSF] = 0x000003ff; in gem_reset()
1478 s->regs[R_RXPARTIALSF] = 0x000003ff; in gem_reset()
1479 s->regs[R_MODID] = s->revision; in gem_reset()
1480 s->regs[R_DESCONF] = 0x02D00111; in gem_reset()
1481 s->regs[R_DESCONF2] = 0x2ab10000 | s->jumbo_max_len; in gem_reset()
1482 s->regs[R_DESCONF5] = 0x002f2045; in gem_reset()
1483 s->regs[R_DESCONF6] = R_DESCONF6_DMA_ADDR_64B_MASK; in gem_reset()
1484 s->regs[R_INT_Q1_MASK] = 0x00000CE6; in gem_reset()
1485 s->regs[R_JUMBO_MAX_LEN] = s->jumbo_max_len; in gem_reset()
1487 if (s->num_priority_queues > 1) { in gem_reset()
1488 queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1); in gem_reset()
1489 s->regs[R_DESCONF6] |= queues_mask; in gem_reset()
1493 a = &s->conf.macaddr.a[0]; in gem_reset()
1494 s->regs[R_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24); in gem_reset()
1495 s->regs[R_SPADDR1HI] = a[4] | (a[5] << 8); in gem_reset()
1498 s->sar_active[i] = false; in gem_reset()
1508 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]); in gem_phy_read()
1509 return s->phy_regs[reg_num]; in gem_phy_read()
1522 s->phy_loop = 0; in gem_phy_write()
1527 s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL; in gem_phy_write()
1531 s->phy_loop = 1; in gem_phy_write()
1533 s->phy_loop = 0; in gem_phy_write()
1537 s->phy_regs[reg_num] = val; in gem_phy_write()
1542 uint32_t val = s->regs[R_PHYMNTNC]; in gem_handle_phy_access()
1547 if (phy_addr != s->phy_addr) { in gem_handle_phy_access()
1550 s->regs[R_PHYMNTNC] = FIELD_DP32(val, PHYMNTNC, DATA, 0xffff); in gem_handle_phy_access()
1559 s->regs[R_PHYMNTNC] = FIELD_DP32(val, PHYMNTNC, DATA, in gem_handle_phy_access()
1583 retval = s->regs[offset]; in gem_read()
1595 s->regs[offset] &= ~(s->regs_rtc[offset]); in gem_read()
1598 retval &= ~(s->regs_wo[offset]); in gem_read()
1620 val &= ~(s->regs_ro[offset]); in gem_write()
1622 readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]); in gem_write()
1625 s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly; in gem_write()
1628 s->regs[offset] &= ~(s->regs_w1c[offset] & val); in gem_write()
1634 for (i = 0; i < s->num_priority_queues; ++i) { in gem_write()
1643 for (i = 0; i < s->num_priority_queues; i++) { in gem_write()
1644 s->tx_desc_addr[i] = gem_get_tx_queue_base_addr(s, i); in gem_write()
1647 if (gem_can_receive(qemu_get_queue(s->nic))) { in gem_write()
1648 qemu_flush_queued_packets(qemu_get_queue(s->nic)); in gem_write()
1656 s->rx_desc_addr[0] = val; in gem_write()
1659 s->rx_desc_addr[offset - R_RECEIVE_Q1_PTR + 1] = val; in gem_write()
1662 s->tx_desc_addr[0] = val; in gem_write()
1665 s->tx_desc_addr[offset - R_TRANSMIT_Q1_PTR + 1] = val; in gem_write()
1671 s->regs[R_IMR] &= ~val; in gem_write()
1675 s->regs[R_JUMBO_MAX_LEN] = val & MAX_JUMBO_FRAME_SIZE_MASK; in gem_write()
1678 s->regs[R_INT_Q1_MASK + offset - R_INT_Q1_ENABLE] &= ~val; in gem_write()
1682 s->regs[R_IMR] |= val; in gem_write()
1686 s->regs[R_INT_Q1_MASK + offset - R_INT_Q1_DISABLE] |= val; in gem_write()
1693 s->sar_active[(offset - R_SPADDR1LO) / 2] = false; in gem_write()
1699 s->sar_active[(offset - R_SPADDR1HI) / 2] = true; in gem_write()
1706 DB_PRINT("newval: 0x%08x\n", s->regs[offset]); in gem_write()
1737 address_space_init(&s->dma_as, in gem_realize()
1738 s->dma_mr ? s->dma_mr : get_system_memory(), "dma"); in gem_realize()
1740 if (s->num_priority_queues == 0 || in gem_realize()
1741 s->num_priority_queues > MAX_PRIORITY_QUEUES) { in gem_realize()
1742 error_setg(errp, "Invalid num-priority-queues value: %" PRIx8, in gem_realize()
1743 s->num_priority_queues); in gem_realize()
1745 } else if (s->num_type1_screeners > MAX_TYPE1_SCREENERS) { in gem_realize()
1746 error_setg(errp, "Invalid num-type1-screeners value: %" PRIx8, in gem_realize()
1747 s->num_type1_screeners); in gem_realize()
1749 } else if (s->num_type2_screeners > MAX_TYPE2_SCREENERS) { in gem_realize()
1750 error_setg(errp, "Invalid num-type2-screeners value: %" PRIx8, in gem_realize()
1751 s->num_type2_screeners); in gem_realize()
1755 for (i = 0; i < s->num_priority_queues; ++i) { in gem_realize()
1756 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); in gem_realize()
1760 qemu_macaddr_default_if_unset(&s->conf.macaddr); in gem_realize()
1762 s->nic = qemu_new_nic(&net_gem_info, &s->conf, in gem_realize()
1763 object_get_typename(OBJECT(dev)), dev->id, in gem_realize()
1764 &dev->mem_reentrancy_guard, s); in gem_realize()
1766 if (s->jumbo_max_len > MAX_FRAME_SIZE) { in gem_realize()
1767 error_setg(errp, "jumbo-max-len is greater than %d", in gem_realize()
1780 memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s, in gem_init()
1781 "enet", sizeof(s->regs)); in gem_init()
1783 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); in gem_init()
1805 DEFINE_PROP_UINT32("revision", CadenceGEMState, revision,
1807 DEFINE_PROP_UINT8("phy-addr", CadenceGEMState, phy_addr, BOARD_PHY_ADDRESS),
1808 DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState,
1810 DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState,
1812 DEFINE_PROP_UINT8("num-type2-screeners", CadenceGEMState,
1814 DEFINE_PROP_UINT16("jumbo-max-len", CadenceGEMState,
1824 dc->realize = gem_realize; in gem_class_init()
1826 dc->vmsd = &vmstate_cadence_gem; in gem_class_init()