31 #define ZYNQ_SLCR_ERR_DEBUG 0
39     } while (0)
41 #define XILINX_LOCK_KEY 0x767b
42 #define XILINX_UNLOCK_KEY 0xdf0d
44 REG32(SCL, 0x000)
45 REG32(LOCK, 0x004)
46 REG32(UNLOCK, 0x008)
47 REG32(LOCKSTA, 0x00c)
49 REG32(ARM_PLL_CTRL, 0x100)
50 REG32(DDR_PLL_CTRL, 0x104)
51 REG32(IO_PLL_CTRL, 0x108)
53     FIELD(xxx_PLL_CTRL, PLL_RESET, 0, 1)
58 REG32(PLL_STATUS, 0x10c)
59 REG32(ARM_PLL_CFG, 0x110)
60 REG32(DDR_PLL_CFG, 0x114)
61 REG32(IO_PLL_CFG, 0x118)
63 REG32(ARM_CLK_CTRL, 0x120)
64 REG32(DDR_CLK_CTRL, 0x124)
65 REG32(DCI_CLK_CTRL, 0x128)
66 REG32(APER_CLK_CTRL, 0x12c)
67 REG32(USB0_CLK_CTRL, 0x130)
68 REG32(USB1_CLK_CTRL, 0x134)
69 REG32(GEM0_RCLK_CTRL, 0x138)
70 REG32(GEM1_RCLK_CTRL, 0x13c)
71 REG32(GEM0_CLK_CTRL, 0x140)
72 REG32(GEM1_CLK_CTRL, 0x144)
73 REG32(SMC_CLK_CTRL, 0x148)
74 REG32(LQSPI_CLK_CTRL, 0x14c)
75 REG32(SDIO_CLK_CTRL, 0x150)
76 REG32(UART_CLK_CTRL, 0x154)
77     FIELD(UART_CLK_CTRL, CLKACT0, 0, 1)
81 REG32(SPI_CLK_CTRL, 0x158)
82 REG32(CAN_CLK_CTRL, 0x15c)
83 REG32(CAN_MIOCLK_CTRL, 0x160)
84 REG32(DBG_CLK_CTRL, 0x164)
85 REG32(PCAP_CLK_CTRL, 0x168)
86 REG32(TOPSW_CLK_CTRL, 0x16c)
90     REG32(FPGA ## n ## _THR_CTRL, (start) + 0x4)\
91     REG32(FPGA ## n ## _THR_CNT,  (start) + 0x8)\
92     REG32(FPGA ## n ## _THR_STA,  (start) + 0xc)
93 FPGA_CTRL_REGS(0, 0x170)
94 FPGA_CTRL_REGS(1, 0x180)
95 FPGA_CTRL_REGS(2, 0x190)
96 FPGA_CTRL_REGS(3, 0x1a0)
98 REG32(BANDGAP_TRIP, 0x1b8)
99 REG32(PLL_PREDIVISOR, 0x1c0)
100 REG32(CLK_621_TRUE, 0x1c4)
102 REG32(PSS_RST_CTRL, 0x200)
103     FIELD(PSS_RST_CTRL, SOFT_RST, 0, 1)
104 REG32(DDR_RST_CTRL, 0x204)
105 REG32(TOPSW_RESET_CTRL, 0x208)
106 REG32(DMAC_RST_CTRL, 0x20c)
107 REG32(USB_RST_CTRL, 0x210)
108 REG32(GEM_RST_CTRL, 0x214)
109 REG32(SDIO_RST_CTRL, 0x218)
110 REG32(SPI_RST_CTRL, 0x21c)
111 REG32(CAN_RST_CTRL, 0x220)
112 REG32(I2C_RST_CTRL, 0x224)
113 REG32(UART_RST_CTRL, 0x228)
114 REG32(GPIO_RST_CTRL, 0x22c)
115 REG32(LQSPI_RST_CTRL, 0x230)
116 REG32(SMC_RST_CTRL, 0x234)
117 REG32(OCM_RST_CTRL, 0x238)
118 REG32(FPGA_RST_CTRL, 0x240)
119 REG32(A9_CPU_RST_CTRL, 0x244)
121 REG32(RS_AWDT_CTRL, 0x24c)
122 REG32(RST_REASON, 0x250)
124 REG32(REBOOT_STATUS, 0x258)
125 REG32(BOOT_MODE, 0x25c)
126     FIELD(BOOT_MODE, BOOT_MODE, 0, 4)
128 REG32(APU_CTRL, 0x300)
129 REG32(WDT_CLK_SEL, 0x304)
131 REG32(TZ_DMA_NS, 0x440)
132 REG32(TZ_DMA_IRQ_NS, 0x444)
133 REG32(TZ_DMA_PERIPH_NS, 0x448)
135 REG32(PSS_IDCODE, 0x530)
137 REG32(DDR_URGENT, 0x600)
138 REG32(DDR_CAL_START, 0x60c)
139 REG32(DDR_REF_START, 0x614)
140 REG32(DDR_CMD_STA, 0x618)
141 REG32(DDR_URGENT_SEL, 0x61c)
142 REG32(DDR_DFI_STATUS, 0x620)
144 REG32(MIO, 0x700)
147 REG32(MIO_LOOPBACK, 0x804)
148 REG32(MIO_MST_TRI0, 0x808)
149 REG32(MIO_MST_TRI1, 0x80c)
151 REG32(SD0_WP_CD_SEL, 0x830)
152 REG32(SD1_WP_CD_SEL, 0x834)
154 REG32(LVL_SHFTR_EN, 0x900)
155 REG32(OCM_CFG, 0x910)
157 REG32(CPU_RAM, 0xa00)
159 REG32(IOU, 0xa30)
161 REG32(DMAC_RAM, 0xa50)
163 REG32(AFI0, 0xa60)
164 REG32(AFI1, 0xa6c)
165 REG32(AFI2, 0xa78)
166 REG32(AFI3, 0xa84)
169 REG32(OCM, 0xa90)
171 REG32(DEVCI_RAM, 0xaa0)
173 REG32(CSG_RAM, 0xab0)
175 REG32(GPIOB_CTRL, 0xb00)
176 REG32(GPIOB_CFG_CMOS18, 0xb04)
177 REG32(GPIOB_CFG_CMOS25, 0xb08)
178 REG32(GPIOB_CFG_CMOS33, 0xb0c)
179 REG32(GPIOB_CFG_HSTL, 0xb14)
180 REG32(GPIOB_DRVR_BIAS_CTRL, 0xb18)
182 REG32(DDRIOB, 0xb40)
185 #define ZYNQ_SLCR_MMIO_SIZE     0x1000
221         return 0;  in zynq_slcr_compute_pll()
253     if (((ctrl_reg >> index) & 1u) == 0) {  in zynq_slcr_compute_clock()
254         return 0;  in zynq_slcr_compute_clock()
262      * the 0 value as a bypass (no division).  in zynq_slcr_compute_clock()
302         ps_clk = 0;  in zynq_slcr_compute_clocks()
335     /* 0x100 - 0x11C */  in zynq_slcr_reset_init()
336     s->regs[R_ARM_PLL_CTRL]   = 0x0001A008;  in zynq_slcr_reset_init()
337     s->regs[R_DDR_PLL_CTRL]   = 0x0001A008;  in zynq_slcr_reset_init()
338     s->regs[R_IO_PLL_CTRL]    = 0x0001A008;  in zynq_slcr_reset_init()
339     s->regs[R_PLL_STATUS]     = 0x0000003F;  in zynq_slcr_reset_init()
340     s->regs[R_ARM_PLL_CFG]    = 0x00014000;  in zynq_slcr_reset_init()
341     s->regs[R_DDR_PLL_CFG]    = 0x00014000;  in zynq_slcr_reset_init()
342     s->regs[R_IO_PLL_CFG]     = 0x00014000;  in zynq_slcr_reset_init()
344     /* 0x120 - 0x16C */  in zynq_slcr_reset_init()
345     s->regs[R_ARM_CLK_CTRL]   = 0x1F000400;  in zynq_slcr_reset_init()
346     s->regs[R_DDR_CLK_CTRL]   = 0x18400003;  in zynq_slcr_reset_init()
347     s->regs[R_DCI_CLK_CTRL]   = 0x01E03201;  in zynq_slcr_reset_init()
348     s->regs[R_APER_CLK_CTRL]  = 0x01FFCCCD;  in zynq_slcr_reset_init()
349     s->regs[R_USB0_CLK_CTRL]  = s->regs[R_USB1_CLK_CTRL]  = 0x00101941;  in zynq_slcr_reset_init()
350     s->regs[R_GEM0_RCLK_CTRL] = s->regs[R_GEM1_RCLK_CTRL] = 0x00000001;  in zynq_slcr_reset_init()
351     s->regs[R_GEM0_CLK_CTRL]  = s->regs[R_GEM1_CLK_CTRL]  = 0x00003C01;  in zynq_slcr_reset_init()
352     s->regs[R_SMC_CLK_CTRL]   = 0x00003C01;  in zynq_slcr_reset_init()
353     s->regs[R_LQSPI_CLK_CTRL] = 0x00002821;  in zynq_slcr_reset_init()
354     s->regs[R_SDIO_CLK_CTRL]  = 0x00001E03;  in zynq_slcr_reset_init()
355     s->regs[R_UART_CLK_CTRL]  = 0x00003F03;  in zynq_slcr_reset_init()
356     s->regs[R_SPI_CLK_CTRL]   = 0x00003F03;  in zynq_slcr_reset_init()
357     s->regs[R_CAN_CLK_CTRL]   = 0x00501903;  in zynq_slcr_reset_init()
358     s->regs[R_DBG_CLK_CTRL]   = 0x00000F03;  in zynq_slcr_reset_init()
359     s->regs[R_PCAP_CLK_CTRL]  = 0x00000F01;  in zynq_slcr_reset_init()
361     /* 0x170 - 0x1AC */  in zynq_slcr_reset_init()
364                               = s->regs[R_FPGA3_CLK_CTRL] = 0x00101800;  in zynq_slcr_reset_init()
367                              = s->regs[R_FPGA3_THR_STA] = 0x00010000;  in zynq_slcr_reset_init()
369     /* 0x1B0 - 0x1D8 */  in zynq_slcr_reset_init()
370     s->regs[R_BANDGAP_TRIP]   = 0x0000001F;  in zynq_slcr_reset_init()
371     s->regs[R_PLL_PREDIVISOR] = 0x00000001;  in zynq_slcr_reset_init()
372     s->regs[R_CLK_621_TRUE]   = 0x00000001;  in zynq_slcr_reset_init()
374     /* 0x200 - 0x25C */  in zynq_slcr_reset_init()
375     s->regs[R_FPGA_RST_CTRL]  = 0x01F33F0F;  in zynq_slcr_reset_init()
376     s->regs[R_RST_REASON]     = 0x00000040;  in zynq_slcr_reset_init()
380     /* 0x700 - 0x7D4 */  in zynq_slcr_reset_init()
381     for (i = 0; i < 54; i++) {  in zynq_slcr_reset_init()
382         s->regs[R_MIO + i] = 0x00001601;  in zynq_slcr_reset_init()
385         s->regs[R_MIO + i] = 0x00000601;  in zynq_slcr_reset_init()
388     s->regs[R_MIO_MST_TRI0] = s->regs[R_MIO_MST_TRI1] = 0xFFFFFFFF;  in zynq_slcr_reset_init()
390     s->regs[R_CPU_RAM + 0] = s->regs[R_CPU_RAM + 1] = s->regs[R_CPU_RAM + 3]  in zynq_slcr_reset_init()
392                            = 0x00010101;  in zynq_slcr_reset_init()
393     s->regs[R_CPU_RAM + 2] = s->regs[R_CPU_RAM + 5] = 0x01010101;  in zynq_slcr_reset_init()
394     s->regs[R_CPU_RAM + 6] = 0x00000001;  in zynq_slcr_reset_init()
396     s->regs[R_IOU + 0] = s->regs[R_IOU + 1] = s->regs[R_IOU + 2]  in zynq_slcr_reset_init()
397                        = s->regs[R_IOU + 3] = 0x09090909;  in zynq_slcr_reset_init()
398     s->regs[R_IOU + 4] = s->regs[R_IOU + 5] = 0x00090909;  in zynq_slcr_reset_init()
399     s->regs[R_IOU + 6] = 0x00000909;  in zynq_slcr_reset_init()
401     s->regs[R_DMAC_RAM] = 0x00000009;  in zynq_slcr_reset_init()
403     s->regs[R_AFI0 + 0] = s->regs[R_AFI0 + 1] = 0x09090909;  in zynq_slcr_reset_init()
404     s->regs[R_AFI1 + 0] = s->regs[R_AFI1 + 1] = 0x09090909;  in zynq_slcr_reset_init()
405     s->regs[R_AFI2 + 0] = s->regs[R_AFI2 + 1] = 0x09090909;  in zynq_slcr_reset_init()
406     s->regs[R_AFI3 + 0] = s->regs[R_AFI3 + 1] = 0x09090909;  in zynq_slcr_reset_init()
408                         = s->regs[R_AFI3 + 2] = 0x00000909;  in zynq_slcr_reset_init()
410     s->regs[R_OCM + 0] = 0x01010101;  in zynq_slcr_reset_init()
411     s->regs[R_OCM + 1] = s->regs[R_OCM + 2] = 0x09090909;  in zynq_slcr_reset_init()
413     s->regs[R_DEVCI_RAM] = 0x00000909;  in zynq_slcr_reset_init()
414     s->regs[R_CSG_RAM]   = 0x00000001;  in zynq_slcr_reset_init()
416     s->regs[R_DDRIOB + 0] = s->regs[R_DDRIOB + 1] = s->regs[R_DDRIOB + 2]  in zynq_slcr_reset_init()
417                           = s->regs[R_DDRIOB + 3] = 0x00000e00;  in zynq_slcr_reset_init()
419                           = 0x00000e00;  in zynq_slcr_reset_init()
420     s->regs[R_DDRIOB + 12] = 0x00000021;  in zynq_slcr_reset_init()
428     zynq_slcr_compute_clocks_internal(s, 0);  in zynq_slcr_reset_hold()
535         s->regs[R_SCL] = val & 0x1;  in zynq_slcr_write()
538         if ((val & 0xFFFF) == XILINX_LOCK_KEY) {  in zynq_slcr_write()
539             DB_PRINT("XILINX LOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,  in zynq_slcr_write()
540                 (unsigned)val & 0xFFFF);  in zynq_slcr_write()
543             DB_PRINT("WRONG XILINX LOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",  in zynq_slcr_write()
544                 (int)offset, (unsigned)val & 0xFFFF);  in zynq_slcr_write()
548         if ((val & 0xFFFF) == XILINX_UNLOCK_KEY) {  in zynq_slcr_write()
549             DB_PRINT("XILINX UNLOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,  in zynq_slcr_write()
550                 (unsigned)val & 0xFFFF);  in zynq_slcr_write()
551             s->regs[R_LOCKSTA] = 0;  in zynq_slcr_write()
553             DB_PRINT("WRONG XILINX UNLOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",  in zynq_slcr_write()
554                 (int)offset, (unsigned)val & 0xFFFF);  in zynq_slcr_write()
599     if (s->boot_mode > 0xF) {  in zynq_slcr_realize()