Lines Matching +full:p +full:- +full:384
2 * Non-crypto strength model of the True Random Number Generator
5 * Copyright (c) 2017-2020 Xilinx Inc.
29 #include "hw/misc/xlnx-versal-trng.h"
33 #include "qemu/error-report.h"
34 #include "qemu/guest-random.h"
38 #include "hw/qdev-properties.h"
128 g_autofree char *p = object_get_canonical_path(OBJECT(D)); \
129 qemu_log_mask(LOG_GUEST_ERROR, "%s: " FMT, p, ## __VA_ARGS__); \
134 g_autofree char *p = object_get_canonical_path(OBJECT(D)); \
135 warn_report("%s: " FMT, p, ## __VA_ARGS__); \
140 return s->hw_version < 0x0200; in trng_older_than_v2()
145 if (ARRAY_FIELD_EX32(s->regs, RESET, VAL)) { in trng_in_reset()
148 if (ARRAY_FIELD_EX32(s->regs, CTRL, PRNGSRST)) { in trng_in_reset()
157 return ARRAY_FIELD_EX32(s->regs, CTRL, TSTMODE); in trng_test_enabled()
165 if (!ARRAY_FIELD_EX32(s->regs, CTRL, TRSSEN)) { in trng_trss_enabled()
168 if (!ARRAY_FIELD_EX32(s->regs, OSC_EN, VAL)) { in trng_trss_enabled()
185 bool ext_seed = ARRAY_FIELD_EX32(s->regs, CTRL, PRNGXS); in trng_reseed()
186 bool pers_disabled = ARRAY_FIELD_EX32(s->regs, CTRL, PERSODISABLE); in trng_reseed()
189 U384_U8 = 384 / 8, in trng_reseed()
190 U384_U32 = 384 / 32, in trng_reseed()
208 * be reproducible if reseeded by the same 384-bit seed, as in trng_reseed()
212 * be reproducible if reseeded by a 128-bit test seed, as in trng_reseed()
214 * 3) Truly-random seeding in trng_reseed()
216 * periodically reseeded by a crypto-strength entropy source. in trng_reseed()
224 * This emulation-only mode can only be selected by setting in trng_reseed()
225 * the uint64 property 'forced-prng' to a non-zero value. in trng_reseed()
231 memcpy(gs, &s->regs[R_PER_STRNG_0], U384_U8); in trng_reseed()
235 memcpy(seed, &s->regs[R_EXT_SEED_0], U384_U8); in trng_reseed()
237 trng_seed_128(seed, s->tst_seed[0], s->tst_seed[1]); in trng_reseed()
238 } else if (s->forced_prng_seed) { in trng_reseed()
239 s->forced_prng_count++; in trng_reseed()
240 trng_seed_128(seed, s->forced_prng_count, s->forced_prng_seed); in trng_reseed()
245 g_rand_set_seed_array(s->prng, gs, ARRAY_SIZE(gs)); in trng_reseed()
247 s->rand_count = 0; in trng_reseed()
248 s->rand_reseed = 1ULL << 48; in trng_reseed()
253 if (s->rand_reseed == 0) { in trng_regen()
257 s->rand_reseed--; in trng_regen()
263 ARRAY_FIELD_DP32(s->regs, STATUS, QCNT, 4); in trng_regen()
264 s->rand_count = 256 / 32; in trng_regen()
269 assert(s->rand_count); in trng_rdout()
271 s->rand_count--; in trng_rdout()
272 if (s->rand_count < 4) { in trng_rdout()
273 ARRAY_FIELD_DP32(s->regs, STATUS, QCNT, s->rand_count); in trng_rdout()
276 return g_rand_int(s->prng); in trng_rdout()
281 bool pending = s->regs[R_TRNG_ISR] & ~s->regs[R_TRNG_IMR]; in trng_irq_update()
282 qemu_set_irq(s->irq, pending); in trng_irq_update()
287 XlnxVersalTRng *s = XLNX_VERSAL_TRNG(reg->opaque); in trng_isr_postw()
293 XlnxVersalTRng *s = XLNX_VERSAL_TRNG(reg->opaque); in trng_ier_prew()
296 s->regs[R_TRNG_IMR] &= ~val; in trng_ier_prew()
303 XlnxVersalTRng *s = XLNX_VERSAL_TRNG(reg->opaque); in trng_idr_prew()
306 s->regs[R_TRNG_IMR] |= val; in trng_idr_prew()
314 uint32_t st = s->regs[R_STATUS]; in trng_core_int_update()
315 uint32_t en = s->regs[R_INT_CTRL]; in trng_core_int_update()
329 ARRAY_FIELD_DP32(s->regs, TRNG_ISR, CORE_INT, pending); in trng_core_int_update()
335 XlnxVersalTRng *s = XLNX_VERSAL_TRNG(reg->opaque); in trng_int_ctrl_postw()
349 s->regs[R_STATUS] &= ~clr_mask; in trng_int_ctrl_postw()
355 ARRAY_FIELD_DP32(s->regs, STATUS, DONE, true); in trng_done()
371 !ARRAY_FIELD_EX32(s->regs, CTRL, QERTUEN)) { in trng_fault_event_set()
374 ARRAY_FIELD_DP32(s->regs, STATUS, CERTF, true); in trng_fault_event_set()
380 ARRAY_FIELD_DP32(s->regs, STATUS, DTF, true); in trng_fault_event_set()
391 s->rand_count = 0; in trng_soft_reset()
392 s->regs[R_STATUS] = 0; in trng_soft_reset()
394 ARRAY_FIELD_DP32(s->regs, TRNG_ISR, CORE_INT, 0); in trng_soft_reset()
399 XlnxVersalTRng *s = XLNX_VERSAL_TRNG(reg->opaque); in trng_ctrl_postw()
426 XlnxVersalTRng *s = XLNX_VERSAL_TRNG(reg->opaque); in trng_ctrl4_postw()
434 s->tst_seed[1] <<= 1; in trng_ctrl4_postw()
435 s->tst_seed[1] |= s->tst_seed[0] >> 63; in trng_ctrl4_postw()
436 s->tst_seed[0] <<= 1; in trng_ctrl4_postw()
437 s->tst_seed[0] |= val64 & 1; in trng_ctrl4_postw()
445 XlnxVersalTRng *s = XLNX_VERSAL_TRNG(reg->opaque); in trng_core_out_postr()
446 bool oneshot = ARRAY_FIELD_EX32(s->regs, CTRL, SINGLEGENMODE); in trng_core_out_postr()
447 bool start = ARRAY_FIELD_EX32(s->regs, CTRL, PRNGSTART); in trng_core_out_postr()
455 if (s->rand_count == 0) { in trng_core_out_postr()
463 if (!oneshot && start && s->rand_count <= 3) { in trng_core_out_postr()
474 s->forced_prng_count = 0; in trng_reset()
476 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { in trng_reset()
477 register_reset(&s->regs_info[i]); in trng_reset()
485 XlnxVersalTRng *s = XLNX_VERSAL_TRNG(reg->opaque); in trng_reset_prew()
487 if (!ARRAY_FIELD_EX32(s->regs, RESET, VAL) && in trng_reset_prew()
514 XlnxVersalTRng *s = XLNX_VERSAL_TRNG(reg_array->r[0]->opaque); in trng_register_write()
612 s->reg_array = in trng_init()
615 s->regs_info, s->regs, in trng_init()
620 sysbus_init_mmio(sbd, &s->reg_array->mem); in trng_init()
621 sysbus_init_irq(sbd, &s->irq); in trng_init()
623 s->prng = g_rand_new(); in trng_init()
630 register_finalize_block(s->reg_array); in trng_finalize()
631 g_rand_free(s->prng); in trng_finalize()
632 s->prng = NULL; in trng_finalize()
664 DEFINE_PROP_UINT64("forced-prng", XlnxVersalTRng, forced_prng_seed, 0),
665 DEFINE_PROP_UINT32("hw-version", XlnxVersalTRng, hw_version, 0x0200),
666 DEFINE_PROP("fips-fault-events", XlnxVersalTRng, forced_faults,
691 dc->vmsd = &vmstate_trng; in trng_class_init()
692 rc->phases.hold = trng_reset_hold; in trng_class_init()