Lines Matching full:reset
2 * QEMU model of the Clock-Reset-LPD (CRL).
101 /* A single register fans out to all ADMA reset inputs. */ in crl_rst_adma_prew()
103 REGFIELD_RESET(dev, s, RST_ADMA, RESET, val64, s->cfg.adma[i]); in crl_rst_adma_prew()
112 REGFIELD_RESET(dev, s, RST_UART0, RESET, val64, s->cfg.uart[0]); in crl_rst_uart0_prew()
120 REGFIELD_RESET(dev, s, RST_UART1, RESET, val64, s->cfg.uart[1]); in crl_rst_uart1_prew()
128 REGFIELD_RESET(dev, s, RST_GEM0, RESET, val64, s->cfg.gem[0]); in crl_rst_gem0_prew()
136 REGFIELD_RESET(dev, s, RST_GEM1, RESET, val64, s->cfg.gem[1]); in crl_rst_gem1_prew()
144 REGFIELD_RESET(dev, s, RST_USB0, RESET, val64, s->cfg.usb); in crl_rst_usb_prew()
154 .reset = 0x1,
162 .reset = 0x1,
165 .reset = 0x24809,
168 .reset = 0x2000000,
173 .reset = R_PLL_STATUS_RPLL_STABLE_MASK |
178 .reset = 0x2000100,
181 .reset = 0x6000300,
184 .reset = 0x2000800,
187 .reset = 0xe000300,
190 .reset = 0x2000500,
193 .reset = 0xe000a00,
196 .reset = 0xe000a00,
199 .reset = 0x300,
202 .reset = 0x2001900,
205 .reset = 0xc00,
208 .reset = 0xc00,
211 .reset = 0x600,
214 .reset = 0x600,
217 .reset = 0xc00,
220 .reset = 0xc00,
223 .reset = 0xc00,
226 .reset = 0xc00,
229 .reset = 0x300,
232 .reset = 0x2000c00,
236 .reset = 0xf04,
239 .reset = 0x300,
242 .reset = 0x300,
245 .reset = 0x3c00,
248 .reset = 0x17,
252 .reset = 0x1,
255 .reset = 0x1,
258 .reset = 0x1,
261 .reset = 0x1,
263 .reset = 0x1,
266 .reset = 0x1,
269 .reset = 0x1,
272 .reset = 0x1,
274 .reset = 0x1,
276 .reset = 0x1,
278 .reset = 0x1,
280 .reset = 0x1,
282 .reset = 0x1,
284 .reset = 0x33,
287 .reset = 0x1,
289 .reset = 0xf,
291 .reset = 0x1,
293 .reset = 0x1,
297 .reset = 0x3,
299 .reset = 0x1,