Lines Matching +full:0 +full:xc00
26 #define XLNX_VERSAL_CRL_ERR_DEBUG 0
48 return 0; in crl_enable_prew()
58 return 0; in crl_disable_prew()
91 REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU0, val64, s->cfg.cpu_r5[0]); in crl_rst_r5_prew()
102 for (i = 0; i < ARRAY_SIZE(s->cfg.adma); i++) { in crl_rst_adma_prew()
112 REGFIELD_RESET(dev, s, RST_UART0, RESET, val64, s->cfg.uart[0]); in crl_rst_uart0_prew()
128 REGFIELD_RESET(dev, s, RST_GEM0, RESET, val64, s->cfg.gem[0]); in crl_rst_gem0_prew()
151 .w1c = 0x1,
154 .reset = 0x1,
155 .ro = 0x1,
162 .reset = 0x1,
163 .rsvd = 0xe,
165 .reset = 0x24809,
166 .rsvd = 0xf88c00f6,
168 .reset = 0x2000000,
169 .rsvd = 0x1801210,
171 .rsvd = 0x7e330000,
175 .rsvd = 0xfa,
176 .ro = 0x5,
178 .reset = 0x2000100,
179 .rsvd = 0xfdfc00ff,
181 .reset = 0x6000300,
182 .rsvd = 0xf9fc00f8,
184 .reset = 0x2000800,
185 .rsvd = 0xfdfc00f8,
187 .reset = 0xe000300,
188 .rsvd = 0xe1fc00f8,
190 .reset = 0x2000500,
191 .rsvd = 0xfdfc00f8,
193 .reset = 0xe000a00,
194 .rsvd = 0xf1fc00f8,
196 .reset = 0xe000a00,
197 .rsvd = 0xf1fc00f8,
199 .reset = 0x300,
200 .rsvd = 0xfdfc00f8,
202 .reset = 0x2001900,
203 .rsvd = 0xfdfc00f8,
205 .reset = 0xc00,
206 .rsvd = 0xfdfc00f8,
208 .reset = 0xc00,
209 .rsvd = 0xfdfc00f8,
211 .reset = 0x600,
212 .rsvd = 0xfdfc00f8,
214 .reset = 0x600,
215 .rsvd = 0xfdfc00f8,
217 .reset = 0xc00,
218 .rsvd = 0xfdfc00f8,
220 .reset = 0xc00,
221 .rsvd = 0xfdfc00f8,
223 .reset = 0xc00,
224 .rsvd = 0xfdfc00f8,
226 .reset = 0xc00,
227 .rsvd = 0xfdfc00f8,
229 .reset = 0x300,
230 .rsvd = 0xfdfc00f8,
232 .reset = 0x2000c00,
233 .rsvd = 0xfdfc00f8,
236 .reset = 0xf04,
237 .rsvd = 0xfffc00f8,
239 .reset = 0x300,
240 .rsvd = 0xfdfc00f8,
242 .reset = 0x300,
243 .rsvd = 0xfdfc00f8,
245 .reset = 0x3c00,
246 .rsvd = 0xfdfc00f8,
248 .reset = 0x17,
249 .rsvd = 0x8,
252 .reset = 0x1,
255 .reset = 0x1,
258 .reset = 0x1,
261 .reset = 0x1,
263 .reset = 0x1,
266 .reset = 0x1,
269 .reset = 0x1,
272 .reset = 0x1,
274 .reset = 0x1,
276 .reset = 0x1,
278 .reset = 0x1,
280 .reset = 0x1,
282 .reset = 0x1,
284 .reset = 0x33,
285 .rsvd = 0xcc,
287 .reset = 0x1,
289 .reset = 0xf,
291 .reset = 0x1,
293 .reset = 0x1,
297 .reset = 0x3,
299 .reset = 0x1,
300 .rsvd = 0xf8,
309 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { in crl_reset_enter()
347 for (i = 0; i < ARRAY_SIZE(s->cfg.cpu_r5); ++i) { in crl_init()
354 for (i = 0; i < ARRAY_SIZE(s->cfg.adma); ++i) { in crl_init()
361 for (i = 0; i < ARRAY_SIZE(s->cfg.uart); ++i) { in crl_init()
368 for (i = 0; i < ARRAY_SIZE(s->cfg.gem); ++i) { in crl_init()