Lines Matching refs:clock_muxes
422 s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT].src]; in rcc_update_cr_register()
550 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_MCO], false); in rcc_update_cfgr_register()
552 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_MCO], in rcc_update_cfgr_register()
562 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_MCO], false); in rcc_update_cfgr_register()
565 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_MCO], false); in rcc_update_cfgr_register()
567 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_MCO], true); in rcc_update_cfgr_register()
568 clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_MCO], in rcc_update_cfgr_register()
579 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_PCLK2], in rcc_update_cfgr_register()
582 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_PCLK2], in rcc_update_cfgr_register()
589 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_PCLK1], in rcc_update_cfgr_register()
592 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_PCLK1], in rcc_update_cfgr_register()
599 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_HCLK], in rcc_update_cfgr_register()
602 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_HCLK], in rcc_update_cfgr_register()
608 clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_SYSCLK], in rcc_update_cfgr_register()
617 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \ in rcc_update_ahb1enr()
633 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \ in rcc_update_ahb2enr()
658 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \ in rcc_update_ahb3enr()
670 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \ in rcc_update_apb1enr()
673 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \ in rcc_update_apb1enr()
716 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \ in rcc_update_apb2enr()
812 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT], 1, (val + 1)); in rcc_update_pllcfgr()
817 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT], false); in rcc_update_pllcfgr()
819 clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT], val - 1); in rcc_update_pllcfgr()
820 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT], true); in rcc_update_pllcfgr()
827 clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \ in rcc_update_ccipr()
857 clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_LSCO], val); in rcc_update_bdcr()
860 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_LSCO], val); in rcc_update_bdcr()
869 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_RTC], val); in rcc_update_bdcr()
872 clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_LCD_AND_RTC_COMMON], val); in rcc_update_bdcr()
1276 &s->clock_muxes[i], in stm32l4x5_rcc_init()
1278 set_clock_mux_init_info(&s->clock_muxes[i], i); in stm32l4x5_rcc_init()
1283 qdev_alias_clock(DEVICE(&s->clock_muxes[i]), "out", DEVICE(obj), alias); in stm32l4x5_rcc_init()
1322 [RCC_CLOCK_MUX_SRC_SYSCLK] = s->clock_muxes[RCC_CLOCK_MUX_SYSCLK].out, in connect_mux_sources()
1323 [RCC_CLOCK_MUX_SRC_HCLK] = s->clock_muxes[RCC_CLOCK_MUX_HCLK].out, in connect_mux_sources()
1324 [RCC_CLOCK_MUX_SRC_PCLK1] = s->clock_muxes[RCC_CLOCK_MUX_PCLK1].out, in connect_mux_sources()
1325 [RCC_CLOCK_MUX_SRC_PCLK2] = s->clock_muxes[RCC_CLOCK_MUX_PCLK2].out, in connect_mux_sources()
1326 [RCC_CLOCK_MUX_SRC_HSE_OVER_32] = s->clock_muxes[RCC_CLOCK_MUX_HSE_OVER_32].out, in connect_mux_sources()
1328 s->clock_muxes[RCC_CLOCK_MUX_LCD_AND_RTC_COMMON].out, in connect_mux_sources()
1402 clock_set_source(pll->in, s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT].out); in stm32l4x5_rcc_realize()
1410 RccClockMuxState *clock_mux = &s->clock_muxes[i]; in stm32l4x5_rcc_realize()