hw/misc/stm32l4x5_exti.c

4  * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5  * Copyright (c) 2023 Samuel Tardieu <samuel.tardieu@telecom-paris.fr>
6  * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
8  * SPDX-License-Identifier: GPL-2.0-or-later
11  * See the COPYING file in the top-level directory.
21  * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
22  * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
84         s->imr[bank] = exti_romask[bank];  in stm32l4x5_exti_reset_hold()
85         s->emr[bank] = 0x00000000;  in stm32l4x5_exti_reset_hold()
86         s->rtsr[bank] = 0x00000000;  in stm32l4x5_exti_reset_hold()
87         s->ftsr[bank] = 0x00000000;  in stm32l4x5_exti_reset_hold()
88         s->swier[bank] = 0x00000000;  in stm32l4x5_exti_reset_hold()
89         s->pr[bank] = 0x00000000;  in stm32l4x5_exti_reset_hold()
90         s->irq_levels[bank] = 0x00000000;  in stm32l4x5_exti_reset_hold()
102     /* Shift the value to enable access in x2 registers. */  in stm32l4x5_exti_set_irq()
105     if (level == extract32(s->irq_levels[bank], irq, 1)) {  in stm32l4x5_exti_set_irq()
106         /* No change in IRQ line state: do nothing */  in stm32l4x5_exti_set_irq()
109     s->irq_levels[bank] = deposit32(s->irq_levels[bank], irq, 1, level);  in stm32l4x5_exti_set_irq()
112     if (!extract32(s->imr[bank], irq, 1)) {  in stm32l4x5_exti_set_irq()
116     /* In case of a direct line interrupt */  in stm32l4x5_exti_set_irq()
118         qemu_set_irq(s->irq[oirq], level);  in stm32l4x5_exti_set_irq()
123     if ((level && extract32(s->rtsr[bank], irq, 1)) ||  in stm32l4x5_exti_set_irq()
124         (!level && extract32(s->ftsr[bank], irq, 1))) {  in stm32l4x5_exti_set_irq()
126         s->pr[bank] |= 1 << irq;  in stm32l4x5_exti_set_irq()
127         qemu_irq_pulse(s->irq[oirq]);  in stm32l4x5_exti_set_irq()
141         r = s->imr[bank];  in stm32l4x5_exti_read()
145         r = s->emr[bank];  in stm32l4x5_exti_read()
149         r = s->rtsr[bank];  in stm32l4x5_exti_read()
153         r = s->ftsr[bank];  in stm32l4x5_exti_read()
157         r = s->swier[bank];  in stm32l4x5_exti_read()
161         r = s->pr[bank];  in stm32l4x5_exti_read()
187         s->imr[bank] = val64 & valid_mask(bank);  in stm32l4x5_exti_write()
191         s->emr[bank] = val64 & valid_mask(bank);  in stm32l4x5_exti_write()
195         s->rtsr[bank] = val64 & configurable_mask(bank);  in stm32l4x5_exti_write()
199         s->ftsr[bank] = val64 & configurable_mask(bank);  in stm32l4x5_exti_write()
204         const uint32_t pend = set & ~s->swier[bank] & s->imr[bank] &  in stm32l4x5_exti_write()
205                               ~s->pr[bank];  in stm32l4x5_exti_write()
206         s->swier[bank] = set;  in stm32l4x5_exti_write()
207         s->pr[bank] |= pend;  in stm32l4x5_exti_write()
210                 qemu_irq_pulse(s->irq[i + 32 * bank]);  in stm32l4x5_exti_write()
217         const uint32_t cleared = s->pr[bank] & val64 & configurable_mask(bank);  in stm32l4x5_exti_write()
219         s->pr[bank] &= ~cleared;  in stm32l4x5_exti_write()
221         s->swier[bank] &= ~cleared;  in stm32l4x5_exti_write()
237     .impl.unaligned = false,
240     .valid.unaligned = false,
248         sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]);  in stm32l4x5_exti_init()
251     memory_region_init_io(&s->mmio, obj, &stm32l4x5_exti_ops, s,  in stm32l4x5_exti_init()
253     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);  in stm32l4x5_exti_init()
279     dc->vmsd = &vmstate_stm32l4x5_exti;  in stm32l4x5_exti_class_init()
280     rc->phases.hold = stm32l4x5_exti_reset_hold;  in stm32l4x5_exti_class_init()