hw/misc/npcm_clk.c

213     NPCM7xxClockPLLState *s = opaque;
214     uint32_t con = s->clk->regs[s->reg];
219         freq = clock_get_hz(s->clock_in);
227     clock_update_hz(s->clock_out, freq);
232     NPCM7xxClockSELState *s = opaque;
233     uint32_t index = extract32(s->clk->regs[NPCM7XX_CLK_CLKSEL], s->offset,
234             s->len);
236     if (index >= s->input_size) {
238                       "%s: SEL index: %u out of range\n",
242     clock_update_hz(s->clock_out, clock_get_hz(s->clock_in[index]));
247     NPCM7xxClockDividerState *s = opaque;
250     freq = s->divide(s);
251     clock_update_hz(s->clock_out, freq);
254 static uint32_t divide_by_constant(NPCM7xxClockDividerState *s)
256     return clock_get_hz(s->clock_in) / s->divisor;
259 static uint32_t divide_by_reg_divisor(NPCM7xxClockDividerState *s)
261     return clock_get_hz(s->clock_in) /
262             (extract32(s->clk->regs[s->reg], s->offset, s->len) + 1);
265 static uint32_t divide_by_reg_divisor_times_2(NPCM7xxClockDividerState *s)
267     return divide_by_reg_divisor(s) / 2;
270 static uint32_t shift_by_reg_divisor(NPCM7xxClockDividerState *s)
272     return clock_get_hz(s->clock_in) >>
273         extract32(s->clk->regs[s->reg], s->offset, s->len);
357     uint32_t (*divide)(NPCM7xxClockDividerState *s);
706         g_autofree char *s = g_strdup_printf("clock-in[%d]", i);
707         sel->clock_in[i] = qdev_init_clock_in(DEVICE(sel), s,
821     NPCMCLKState *s = opaque;
822     NPCMCLKClass *c = NPCM_CLK_GET_CLASS(s);
828                       "%s: offset 0x%04" HWADDR_PRIx " out of range\n",
836                       "%s: register @ 0x%04" HWADDR_PRIx " is write-only\n",
842         value = (now_ns - s->ref_ns) / NANOSECONDS_PER_SECOND;
853         value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_CLOCK_REF_HZ;
857         value = s->regs[reg];
870     NPCMCLKState *s = opaque;
871     NPCMCLKClass *c = NPCM_CLK_GET_CLASS(s);
878                       "%s: offset 0x%04" HWADDR_PRIx " out of range\n",
885         qemu_log_mask(LOG_UNIMP, "%s: SW reset not implemented: 0x%02x\n",
910             npcm7xx_clk_update_pll(&s->plls[find_pll_by_reg(reg)]);
915         npcm7xx_clk_update_all_sels(s);
921         npcm7xx_clk_update_all_dividers(s);
926                       "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
931     s->regs[reg] = value;
947                 "%s: only CPU reset is implemented. (requested 0x%" PRIx32")\n",
965     NPCMCLKState *s = NPCM_CLK(obj);
966     NPCMCLKClass *c = NPCM_CLK_GET_CLASS(s);
969     g_assert(sizeof(s->regs) >= sizeof_regs);
970     memcpy(s->regs, c->cold_reset_values, sizeof_regs);
971     s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
972     npcm7xx_clk_update_all_clocks(s);
979 static void npcm7xx_clk_init_clock_hierarchy(NPCMCLKState *s)
983     s->clkref = qdev_init_clock_in(DEVICE(s), "clkref", NULL, NULL, 0);
991         object_initialize_child(OBJECT(s), pll_init_info_list[i].name,
992                 &s->plls[i], TYPE_NPCM7XX_CLOCK_PLL);
993         npcm7xx_init_clock_pll(&s->plls[i], s,
997         object_initialize_child(OBJECT(s), sel_init_info_list[i].name,
998                 &s->sels[i], TYPE_NPCM7XX_CLOCK_SEL);
999         npcm7xx_init_clock_sel(&s->sels[i], s,
1003         object_initialize_child(OBJECT(s), divider_init_info_list[i].name,
1004                 &s->dividers[i], TYPE_NPCM7XX_CLOCK_DIVIDER);
1005         npcm7xx_init_clock_divider(&s->dividers[i], s,
1010     npcm7xx_connect_clocks(s);
1012     clock_update_hz(s->clkref, NPCM7XX_CLOCK_REF_HZ);
1017     NPCMCLKState *s = NPCM_CLK(obj);
1019     memory_region_init_io(&s->iomem, obj, &npcm_clk_ops, s,
1021     sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
1038     NPCMCLKState *s = NPCM_CLK(dev);
1040     qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
1042     npcm7xx_clk_init_clock_hierarchy(s);
1046         if (!qdev_realize(DEVICE(&s->plls[i]), NULL, errp)) {
1051         if (!qdev_realize(DEVICE(&s->sels[i]), NULL, errp)) {
1056         if (!qdev_realize(DEVICE(&s->dividers[i]), NULL, errp)) {