2  * Nuvoton NPCM7xx PWM Module
64 /* Offset of each PWM channel's prescaler in the PPR register. */
66 /* Offset of each PWM channel's clock selector in the CSR register. */
68 /* Offset of each PWM channel's control variable in the PCR register. */
161             npcm7xx_pwm_update_freq(&s->pwm[i]);  in npcm7xx_pwm_write_ppr()
175             npcm7xx_pwm_update_freq(&s->pwm[i]);  in npcm7xx_pwm_write_csr()
190         p = &s->pwm[i];  in npcm7xx_pwm_write_pcr()
195          * We only run a PWM channel with toggle mode. Single-shot mode does not  in npcm7xx_pwm_write_pcr()
200                 /* Re-run this PWM channel if inverted changed. */  in npcm7xx_pwm_write_pcr()
206                 /* Run this PWM channel. */  in npcm7xx_pwm_write_pcr()
212             /* Clear this PWM channel. */  in npcm7xx_pwm_write_pcr()
295         value = s->pwm[npcm7xx_cnr_index(offset)].cnr;  in npcm7xx_pwm_read()
302         value = s->pwm[npcm7xx_cmr_index(offset)].cmr;  in npcm7xx_pwm_read()
309         value = s->pwm[npcm7xx_pdr_index(offset)].pdr;  in npcm7xx_pwm_read()
316         value = s->pwm[npcm7xx_pwdr_index(offset)].pwdr;  in npcm7xx_pwm_read()
363         p = &s->pwm[npcm7xx_cnr_index(offset)];  in npcm7xx_pwm_write()
378         p = &s->pwm[npcm7xx_cmr_index(offset)];  in npcm7xx_pwm_write()
456         NPCM7xxPWM *p = &s->pwm[i];  in npcm7xx_pwm_enter_reset()
477         qemu_irq_lower(s->pwm[i].irq);  in npcm7xx_pwm_hold_reset()
487     QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->pwm) != NPCM7XX_PWM_PER_MODULE);  in npcm7xx_pwm_init()
489         NPCM7xxPWM *p = &s->pwm[i];  in npcm7xx_pwm_init()
502                 &s->pwm[i].freq, OBJ_PROP_FLAG_READ);  in npcm7xx_pwm_init()
504                 &s->pwm[i].duty, OBJ_PROP_FLAG_READ);  in npcm7xx_pwm_init()
511     .name = "npcm7xx-pwm",
529     .name = "npcm7xx-pwm-module",
534         VMSTATE_STRUCT_ARRAY(pwm, NPCM7xxPWMState,
551     dc->desc = "NPCM7xx PWM Controller";  in npcm7xx_pwm_class_init()