Lines Matching +full:imx7 +full:- +full:reset

2  * IMX7 System Reset Controller
4 * Copyright (c) 2023 Jean-Christophe Dubois <jcd@tribudubois.net>
7 * See the COPYING file in the top-level directory.
16 #include "qemu/main-loop.h"
18 #include "target/arm/arm-powerctl.h"
97 memset(s->regs, 0, sizeof(s->regs)); in imx7_src_reset()
99 /* Set reset values */ in imx7_src_reset()
100 s->regs[SRC_SCR] = 0xA0; in imx7_src_reset()
101 s->regs[SRC_SRSR] = 0x1; in imx7_src_reset()
102 s->regs[SRC_SIMR] = 0x1F; in imx7_src_reset()
112 value = s->regs[index]; in imx7_src_read()
125 * The reset is asynchronous so we need to defer clearing the reset
137 IMX7SRCState *s = ri->s; in imx7_clear_reset_bit()
141 s->regs[SRC_A7RCR0] = deposit32(s->regs[SRC_A7RCR0], ri->reset_bit, 1, 0); in imx7_clear_reset_bit()
143 trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0]); in imx7_clear_reset_bit()
160 ri->s = s; in imx7_defer_clear_reset_bit()
161 ri->reset_bit = reset_shift; in imx7_defer_clear_reset_bit()
181 trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0]); in imx7_src_write()
183 change_mask = s->regs[index] ^ (uint32_t)current_value; in imx7_src_write()
195 s->regs[index] = current_value; in imx7_src_write()
199 * On real hardware when the system reset controller starts a in imx7_src_write()
210 arm_set_cpu_on(1, s->regs[SRC_GPR3], s->regs[SRC_GPR4], in imx7_src_write()
216 /* We clear the reset bits as the processor changed state */ in imx7_src_write()
220 s->regs[index] = current_value; in imx7_src_write()
223 s->regs[index] = current_value; in imx7_src_write()
249 memory_region_init_io(&s->iomem, OBJECT(dev), &imx7_src_ops, s, in imx7_src_realize()
251 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); in imx7_src_realize()
258 dc->realize = imx7_src_realize; in imx7_src_class_init()
260 dc->vmsd = &vmstate_imx7_src; in imx7_src_class_init()
261 dc->desc = "i.MX6 System Reset Controller"; in imx7_src_class_init()