Lines Matching +full:0 +full:x00000bff
35 * MCC (version 0, implementation 0) SS-600MP
36 * EMC (version 0, implementation 1) SS-10
37 * SMC (version 0, implementation 2) SS-10SX and SS-20
44 #define ECC_MCC 0x00000000
45 #define ECC_EMC 0x10000000
46 #define ECC_SMC 0x20000000
49 #define ECC_MER 0 /* Memory Enable Register */
53 #define ECC_MFAR0 4 /* Memory Fault Address Register 0 */
56 #define ECC_ECR0 7 /* Event Count Register 0 */
60 #define ECC_MER_EE 0x00000001 /* Enable ECC checking */
61 #define ECC_MER_EI 0x00000002 /* Enable Interrupts on
63 #define ECC_MER_MRR0 0x00000004 /* SIMM 0 */
64 #define ECC_MER_MRR1 0x00000008 /* SIMM 1 */
65 #define ECC_MER_MRR2 0x00000010 /* SIMM 2 */
66 #define ECC_MER_MRR3 0x00000020 /* SIMM 3 */
67 #define ECC_MER_MRR4 0x00000040 /* SIMM 4 */
68 #define ECC_MER_MRR5 0x00000080 /* SIMM 5 */
69 #define ECC_MER_MRR6 0x00000100 /* SIMM 6 */
70 #define ECC_MER_MRR7 0x00000200 /* SIMM 7 */
71 #define ECC_MER_REU 0x00000100 /* Memory Refresh Enable (600MP) */
72 #define ECC_MER_MRR 0x000003fc /* MRR mask */
73 #define ECC_MER_A 0x00000400 /* Memory controller addr map select */
74 #define ECC_MER_DCI 0x00000800 /* Disables Coherent Invalidate ACK */
75 #define ECC_MER_VER 0x0f000000 /* Version */
76 #define ECC_MER_IMPL 0xf0000000 /* Implementation */
77 #define ECC_MER_MASK_0 0x00000103 /* Version 0 (MCC) mask */
78 #define ECC_MER_MASK_1 0x00000bff /* Version 1 (EMC) mask */
79 #define ECC_MER_MASK_2 0x00000bff /* Version 2 (SMC) mask */
82 #define ECC_MDR_RRI 0x000003ff /* Refresh Request Interval */
83 #define ECC_MDR_MI 0x00001c00 /* MIH Delay */
84 #define ECC_MDR_CI 0x0000e000 /* Coherent Invalidate Delay */
85 #define ECC_MDR_MDL 0x001f0000 /* MBus Master arbitration delay */
86 #define ECC_MDR_MDH 0x03e00000 /* MBus Master arbitration delay */
87 #define ECC_MDR_GAD 0x7c000000 /* Graphics Arbitration Delay */
88 #define ECC_MDR_RSC 0x80000000 /* Refresh load control */
89 #define ECC_MDR_MASK 0x7fffffff
92 #define ECC_MFSR_CE 0x00000001 /* Correctable error */
93 #define ECC_MFSR_BS 0x00000002 /* C2 graphics bad slot access */
94 #define ECC_MFSR_TO 0x00000004 /* Timeout on write */
95 #define ECC_MFSR_UE 0x00000008 /* Uncorrectable error */
96 #define ECC_MFSR_DW 0x000000f0 /* Index of double word in block */
97 #define ECC_MFSR_SYND 0x0000ff00 /* Syndrome for correctable error */
98 #define ECC_MFSR_ME 0x00010000 /* Multiple errors */
99 #define ECC_MFSR_C2ERR 0x00020000 /* C2 graphics error */
101 /* ECC fault address register 0 */
102 #define ECC_MFAR0_PADDR 0x0000000f /* PA[32-35] */
103 #define ECC_MFAR0_TYPE 0x000000f0 /* Transaction type */
104 #define ECC_MFAR0_SIZE 0x00000700 /* Transaction size */
105 #define ECC_MFAR0_CACHE 0x00000800 /* Mapped cacheable */
106 #define ECC_MFAR0_LOCK 0x00001000 /* Error occurred in atomic cycle */
107 #define ECC_MFAR0_BMODE 0x00002000 /* Boot mode */
108 #define ECC_MFAR0_VADDR 0x003fc000 /* VA[12-19] (superset bits) */
109 #define ECC_MFAR0_S 0x08000000 /* Supervisor mode */
110 #define ECC_MFARO_MID 0xf0000000 /* Module ID */
113 #define ECC_DR_CBX 0x00000001
114 #define ECC_DR_CB0 0x00000002
115 #define ECC_DR_CB1 0x00000004
116 #define ECC_DR_CB2 0x00000008
117 #define ECC_DR_CB4 0x00000010
118 #define ECC_DR_CB8 0x00000020
119 #define ECC_DR_CB16 0x00000040
120 #define ECC_DR_CB32 0x00000080
121 #define ECC_DR_DMODE 0x00000c00
189 uint32_t ret = 0; in ecc_mem_read()
293 s->regs[ECC_MDR] = 0x20; in ecc_reset()
294 s->regs[ECC_MFSR] = 0; in ecc_reset()
295 s->regs[ECC_VCR] = 0; in ecc_reset()
296 s->regs[ECC_MFAR0] = 0x07c00000; in ecc_reset()
297 s->regs[ECC_MFAR1] = 0; in ecc_reset()
298 s->regs[ECC_DR] = 0; in ecc_reset()
299 s->regs[ECC_ECR0] = 0; in ecc_reset()
300 s->regs[ECC_ECR1] = 0; in ecc_reset()
319 s->regs[0] = s->version; in ecc_realize()