6  * SPDX-License-Identifier: GPL-2.0-or-later
11 #include "qemu/error-report.h"
56         val = xdma->regs[TO_REG(addr)];  in aspeed_xdma_read()
74     if (addr == axc->cmdq_endp) {  in aspeed_xdma_write()
75         xdma->regs[TO_REG(addr)] = val32 & XDMA_BMC_CMDQ_W_MASK;  in aspeed_xdma_write()
76     } else if (addr == axc->cmdq_wrp) {  in aspeed_xdma_write()
78         xdma->regs[idx] = val32 & XDMA_BMC_CMDQ_W_MASK;  in aspeed_xdma_write()
79         xdma->regs[TO_REG(axc->cmdq_rdp)] = xdma->regs[idx];  in aspeed_xdma_write()
83         if (xdma->bmc_cmdq_readp_set) {  in aspeed_xdma_write()
84             xdma->bmc_cmdq_readp_set = 0;  in aspeed_xdma_write()
86             xdma->regs[TO_REG(axc->intr_status)] |= axc->intr_complete;  in aspeed_xdma_write()
88             if (xdma->regs[TO_REG(axc->intr_ctrl)] & axc->intr_complete) {  in aspeed_xdma_write()
89                 qemu_irq_raise(xdma->irq);  in aspeed_xdma_write()
92     } else if (addr == axc->cmdq_rdp) {  in aspeed_xdma_write()
96             xdma->bmc_cmdq_readp_set = 1;  in aspeed_xdma_write()
98     } else if (addr == axc->intr_ctrl) {  in aspeed_xdma_write()
99         xdma->regs[TO_REG(addr)] = val32 & axc->intr_ctrl_mask;  in aspeed_xdma_write()
100     } else if (addr == axc->intr_status) {  in aspeed_xdma_write()
104         if (val32 & axc->intr_complete) {  in aspeed_xdma_write()
105             xdma->regs[idx] &= ~axc->intr_complete;  in aspeed_xdma_write()
106             qemu_irq_lower(xdma->irq);  in aspeed_xdma_write()
109         xdma->regs[TO_REG(addr)] = val32;  in aspeed_xdma_write()
117     .valid.min_access_size = 4,
118     .valid.max_access_size = 4,
126     sysbus_init_irq(sbd, &xdma->irq);  in aspeed_xdma_realize()
127     memory_region_init_io(&xdma->iomem, OBJECT(xdma), &aspeed_xdma_ops, xdma,  in aspeed_xdma_realize()
129     sysbus_init_mmio(sbd, &xdma->iomem);  in aspeed_xdma_realize()
137     xdma->bmc_cmdq_readp_set = 0;  in aspeed_xdma_reset()
138     memset(xdma->regs, 0, ASPEED_XDMA_REG_SIZE);  in aspeed_xdma_reset()
139     xdma->regs[TO_REG(axc->intr_status)] = XDMA_IRQ_ENG_STAT_RESET;  in aspeed_xdma_reset()
141     qemu_irq_lower(xdma->irq);  in aspeed_xdma_reset()
155     DeviceClass *dc = DEVICE_CLASS(klass);  in aspeed_2600_xdma_class_init()  local
158     dc->desc = "ASPEED 2600 XDMA Controller";  in aspeed_2600_xdma_class_init()
160     axc->cmdq_endp = XDMA_AST2600_BMC_CMDQ_ENDP;  in aspeed_2600_xdma_class_init()
161     axc->cmdq_wrp = XDMA_AST2600_BMC_CMDQ_WRP;  in aspeed_2600_xdma_class_init()
162     axc->cmdq_rdp = XDMA_AST2600_BMC_CMDQ_RDP;  in aspeed_2600_xdma_class_init()
163     axc->intr_ctrl = XDMA_AST2600_IRQ_CTRL;  in aspeed_2600_xdma_class_init()
164     axc->intr_ctrl_mask = XDMA_AST2600_IRQ_CTRL_W_MASK;  in aspeed_2600_xdma_class_init()
165     axc->intr_status = XDMA_AST2600_IRQ_STATUS;  in aspeed_2600_xdma_class_init()
166     axc->intr_complete = XDMA_AST2600_IRQ_STATUS_US_COMP |  in aspeed_2600_xdma_class_init()
178     DeviceClass *dc = DEVICE_CLASS(klass);  in aspeed_2500_xdma_class_init()  local
181     dc->desc = "ASPEED 2500 XDMA Controller";  in aspeed_2500_xdma_class_init()
183     axc->cmdq_endp = XDMA_BMC_CMDQ_ENDP;  in aspeed_2500_xdma_class_init()
184     axc->cmdq_wrp = XDMA_BMC_CMDQ_WRP;  in aspeed_2500_xdma_class_init()
185     axc->cmdq_rdp = XDMA_BMC_CMDQ_RDP;  in aspeed_2500_xdma_class_init()
186     axc->intr_ctrl = XDMA_IRQ_ENG_CTRL;  in aspeed_2500_xdma_class_init()
187     axc->intr_ctrl_mask = XDMA_IRQ_ENG_CTRL_W_MASK;  in aspeed_2500_xdma_class_init()
188     axc->intr_status = XDMA_IRQ_ENG_STAT;  in aspeed_2500_xdma_class_init()
189     axc->intr_complete = XDMA_IRQ_ENG_STAT_US_COMP | XDMA_IRQ_ENG_STAT_DS_COMP;  in aspeed_2500_xdma_class_init()
200     DeviceClass *dc = DEVICE_CLASS(klass);  in aspeed_2400_xdma_class_init()  local
203     dc->desc = "ASPEED 2400 XDMA Controller";  in aspeed_2400_xdma_class_init()
205     axc->cmdq_endp = XDMA_BMC_CMDQ_ENDP;  in aspeed_2400_xdma_class_init()
206     axc->cmdq_wrp = XDMA_BMC_CMDQ_WRP;  in aspeed_2400_xdma_class_init()
207     axc->cmdq_rdp = XDMA_BMC_CMDQ_RDP;  in aspeed_2400_xdma_class_init()
208     axc->intr_ctrl = XDMA_IRQ_ENG_CTRL;  in aspeed_2400_xdma_class_init()
209     axc->intr_ctrl_mask = XDMA_IRQ_ENG_CTRL_W_MASK;  in aspeed_2400_xdma_class_init()
210     axc->intr_status = XDMA_IRQ_ENG_STAT;  in aspeed_2400_xdma_class_init()
211     axc->intr_complete = XDMA_IRQ_ENG_STAT_US_COMP | XDMA_IRQ_ENG_STAT_DS_COMP;  in aspeed_2400_xdma_class_init()
222     DeviceClass *dc = DEVICE_CLASS(classp);  in aspeed_xdma_class_init()  local
224     dc->realize = aspeed_xdma_realize;  in aspeed_xdma_class_init()
225     device_class_set_legacy_reset(dc, aspeed_xdma_reset);  in aspeed_xdma_class_init()
226     dc->vmsd = &aspeed_xdma_vmstate;  in aspeed_xdma_class_init()