hw/misc/aspeed_xdma.c

19 #define XDMA_BMC_CMDQ_ADDR         0x10
20 #define XDMA_BMC_CMDQ_ENDP         0x14
21 #define XDMA_BMC_CMDQ_WRP          0x18
22 #define  XDMA_BMC_CMDQ_W_MASK      0x0003FFFF
23 #define XDMA_BMC_CMDQ_RDP          0x1C
24 #define  XDMA_BMC_CMDQ_RDP_MAGIC   0xEE882266
25 #define XDMA_IRQ_ENG_CTRL          0x20
28 #define  XDMA_IRQ_ENG_CTRL_W_MASK  0xBFEFF07F
29 #define XDMA_IRQ_ENG_STAT          0x24
32 #define  XDMA_IRQ_ENG_STAT_RESET   0xF8000000
34 #define XDMA_AST2600_BMC_CMDQ_ADDR   0x14
35 #define XDMA_AST2600_BMC_CMDQ_ENDP   0x18
36 #define XDMA_AST2600_BMC_CMDQ_WRP    0x1c
37 #define XDMA_AST2600_BMC_CMDQ_RDP    0x20
38 #define XDMA_AST2600_IRQ_CTRL        0x38
41 #define  XDMA_AST2600_IRQ_CTRL_W_MASK     0x017003FF
42 #define XDMA_AST2600_IRQ_STATUS      0x3c
46 #define XDMA_MEM_SIZE              0x1000
52     uint32_t val = 0;  in aspeed_xdma_read()
84             xdma->bmc_cmdq_readp_set = 0;  in aspeed_xdma_write()
137     xdma->bmc_cmdq_readp_set = 0;  in aspeed_xdma_reset()
138     memset(xdma->regs, 0, ASPEED_XDMA_REG_SIZE);  in aspeed_xdma_reset()