hw/misc/aspeed_peci.c

2  * Aspeed PECI Controller
7  * file in the top-level directory.
36     trace_aspeed_peci_raise_interrupt(s->regs[R_PECI_INT_CTRL], status);  in aspeed_peci_raise_interrupt()
38     s->regs[R_PECI_INT_STS] = s->regs[R_PECI_INT_CTRL] & status;  in aspeed_peci_raise_interrupt()
39     if (!s->regs[R_PECI_INT_STS]) {  in aspeed_peci_raise_interrupt()
42     qemu_irq_raise(s->irq);  in aspeed_peci_raise_interrupt()
52                       "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",  in aspeed_peci_read()
56     data = s->regs[offset >> 2];  in aspeed_peci_read()
71                       "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",  in aspeed_peci_write()
78         s->regs[R_PECI_INT_STS] &= ~data;  in aspeed_peci_write()
79         if (!s->regs[R_PECI_INT_STS]) {  in aspeed_peci_write()
80             qemu_irq_lower(s->irq);  in aspeed_peci_write()
92         if (s->regs[R_PECI_INT_STS]) {  in aspeed_peci_write()
95                           __func__, s->regs[R_PECI_INT_STS]);  in aspeed_peci_write()
98         s->regs[R_PECI_RD_DATA0] = ASPEED_PECI_CC_RSP_SUCCESS;  in aspeed_peci_write()
99         s->regs[R_PECI_WR_DATA0] = ASPEED_PECI_CC_RSP_SUCCESS;  in aspeed_peci_write()
104         s->regs[offset / sizeof(s->regs[0])] = data;  in aspeed_peci_write()
120     memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_peci_ops, s,  in aspeed_peci_realize()
122     sysbus_init_mmio(sbd, &s->mmio);  in aspeed_peci_realize()
123     sysbus_init_irq(sbd, &s->irq);  in aspeed_peci_realize()
130     memset(s->regs, 0, sizeof(s->regs));  in aspeed_peci_reset()
137     dc->realize = aspeed_peci_realize;  in aspeed_peci_class_init()
139     dc->desc = "Aspeed PECI Controller";  in aspeed_peci_class_init()