Lines Matching refs:mb_clock

48     uint32_t mb_clock[6];  member
73         VMSTATE_UINT32_ARRAY_V(mb_clock, arm_sysctl_state, 6, 4),
108     s->mb_clock[0] = 50000000; /* Static memory clock: 50MHz */  in arm_sysctl_reset()
109     s->mb_clock[1] = 23750000; /* motherboard CLCD clock: 23.75MHz */  in arm_sysctl_reset()
110     s->mb_clock[2] = 24000000; /* IO FPGA peripheral clock: 24MHz */  in arm_sysctl_reset()
111     s->mb_clock[3] = 24000000; /* IO FPGA reserved clock: 24MHz */  in arm_sysctl_reset()
112     s->mb_clock[4] = 24000000; /* System bus global clock: 24MHz */  in arm_sysctl_reset()
113     s->mb_clock[5] = 24000000; /* IO FPGA reserved clock: 24MHz */  in arm_sysctl_reset()
285         if (site == SYS_CFG_SITE_MB && device < ARRAY_SIZE(s->mb_clock)) {  in vexpress_cfgctrl_read()
287             *val = s->mb_clock[device];  in vexpress_cfgctrl_read()
333         if (site == SYS_CFG_SITE_MB && device < ARRAY_SIZE(s->mb_clock)) {  in vexpress_cfgctrl_write()
335             s->mb_clock[device] = val;  in vexpress_cfgctrl_write()