Lines Matching +full:fpga +full:- +full:bridge
30 #include "qemu/guest-random.h"
35 #include "hw/char/serial-mm.h"
51 #include "qemu/host-utils.h"
56 #include "qemu/error-report.h"
60 #include "hw/qdev-clock.h"
82 MemoryRegion iomem_lo; /* 0 - 0x900 */
83 MemoryRegion iomem_hi; /* 0xa00 - 0x100000 */
97 #define TYPE_MIPS_MALTA "mips-malta"
114 /* Malta FPGA */
120 for (i = 7 ; i >= 0 ; i--) { in malta_fpga_update_display_leds()
121 if (s->leds & (1 << i)) { in malta_fpga_update_display_leds()
130 qemu_chr_fe_printf(&s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", in malta_fpga_update_display_leds()
136 trace_malta_fpga_display(s->display_text); in malta_fpga_update_display_ascii()
137 qemu_chr_fe_printf(&s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", in malta_fpga_update_display_ascii()
138 s->display_text); in malta_fpga_update_display_ascii()
145 * 24C01 - 1024 bit (128 x 8)
146 * 24C02 - 2048 bit (256 x 8)
153 fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__)
221 int sz_log2 = MIN(31 - clz32(ram_size), 14); in generate_eeprom_spd()
223 density |= 1 << (sz_log2 - 2); in generate_eeprom_spd()
224 ram_size -= 1 << sz_log2; in generate_eeprom_spd()
296 eeprom->tick, eeprom->scl, eeprom->sda, eeprom->data); in eeprom24c0x_read()
297 return eeprom->sda; in eeprom24c0x_read()
302 if (eeprom->scl && scl && (eeprom->sda != sda)) { in eeprom24c0x_write()
303 logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n", in eeprom24c0x_write()
304 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda, in eeprom24c0x_write()
307 eeprom->tick = 1; in eeprom24c0x_write()
308 eeprom->command = 0; in eeprom24c0x_write()
310 } else if (eeprom->tick == 0 && !eeprom->ack) { in eeprom24c0x_write()
312 logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n", in eeprom24c0x_write()
313 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda); in eeprom24c0x_write()
314 } else if (!eeprom->scl && scl) { in eeprom24c0x_write()
315 logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n", in eeprom24c0x_write()
316 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda); in eeprom24c0x_write()
317 if (eeprom->ack) { in eeprom24c0x_write()
320 eeprom->ack = 0; in eeprom24c0x_write()
321 } else if (eeprom->sda == sda) { in eeprom24c0x_write()
324 if (eeprom->tick < 9) { in eeprom24c0x_write()
325 eeprom->command <<= 1; in eeprom24c0x_write()
326 eeprom->command += bit; in eeprom24c0x_write()
327 eeprom->tick++; in eeprom24c0x_write()
328 if (eeprom->tick == 9) { in eeprom24c0x_write()
329 logout("\tcommand 0x%04x, %s\n", eeprom->command, in eeprom24c0x_write()
331 eeprom->ack = 1; in eeprom24c0x_write()
333 } else if (eeprom->tick < 17) { in eeprom24c0x_write()
334 if (eeprom->command & 1) { in eeprom24c0x_write()
335 sda = ((eeprom->data & 0x80) != 0); in eeprom24c0x_write()
337 eeprom->address <<= 1; in eeprom24c0x_write()
338 eeprom->address += bit; in eeprom24c0x_write()
339 eeprom->tick++; in eeprom24c0x_write()
340 eeprom->data <<= 1; in eeprom24c0x_write()
341 if (eeprom->tick == 17) { in eeprom24c0x_write()
342 eeprom->data = eeprom->contents[eeprom->address]; in eeprom24c0x_write()
344 eeprom->address, eeprom->data); in eeprom24c0x_write()
345 eeprom->ack = 1; in eeprom24c0x_write()
346 eeprom->tick = 0; in eeprom24c0x_write()
348 } else if (eeprom->tick >= 17) { in eeprom24c0x_write()
355 logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom->tick, eeprom->scl, in eeprom24c0x_write()
356 scl, eeprom->sda, sda); in eeprom24c0x_write()
358 eeprom->scl = scl; in eeprom24c0x_write()
359 eeprom->sda = sda; in eeprom24c0x_write()
390 val = s->leds; in malta_fpga_read()
395 val = s->brk; in malta_fpga_read()
402 val = s->gpout; in malta_fpga_read()
410 if (s->i2csel) { in malta_fpga_read()
411 val = s->i2cout; in malta_fpga_read()
419 val = ((s->i2cin & ~1) | eeprom24c0x_read(&spd_eeprom)); in malta_fpga_read()
424 val = s->i2coe; in malta_fpga_read()
429 val = s->i2cout; in malta_fpga_read()
434 val = s->i2csel; in malta_fpga_read()
466 s->leds = val & 0xff; in malta_fpga_write()
472 snprintf(s->display_text, 9, "%08X", (uint32_t)val); in malta_fpga_write()
485 s->display_text[(saddr - 0x00418) >> 3] = (char) val; in malta_fpga_write()
498 s->brk = val & 0xff; in malta_fpga_write()
505 s->gpout = val & 0xff; in malta_fpga_write()
510 s->i2coe = val & 0x03; in malta_fpga_write()
516 s->i2cout = val; in malta_fpga_write()
521 s->i2csel = val & 0x01; in malta_fpga_write()
542 s->leds = 0x00; in malta_fpga_reset()
543 s->brk = 0x0a; in malta_fpga_reset()
544 s->gpout = 0x00; in malta_fpga_reset()
545 s->i2cin = 0x3; in malta_fpga_reset()
546 s->i2coe = 0x0; in malta_fpga_reset()
547 s->i2cout = 0x3; in malta_fpga_reset()
548 s->i2csel = 0x1; in malta_fpga_reset()
550 s->display_text[8] = '\0'; in malta_fpga_reset()
551 snprintf(s->display_text, 9, " "); in malta_fpga_reset()
558 if (event == CHR_EVENT_OPENED && !s->display_inited) { in malta_fgpa_display_event()
559 qemu_chr_fe_printf(&s->display, "\e[HMalta LEDBAR\r\n"); in malta_fgpa_display_event()
560 qemu_chr_fe_printf(&s->display, "+--------+\r\n"); in malta_fgpa_display_event()
561 qemu_chr_fe_printf(&s->display, "+ +\r\n"); in malta_fgpa_display_event()
562 qemu_chr_fe_printf(&s->display, "+--------+\r\n"); in malta_fgpa_display_event()
563 qemu_chr_fe_printf(&s->display, "\n"); in malta_fgpa_display_event()
564 qemu_chr_fe_printf(&s->display, "Malta ASCII\r\n"); in malta_fgpa_display_event()
565 qemu_chr_fe_printf(&s->display, "+--------+\r\n"); in malta_fgpa_display_event()
566 qemu_chr_fe_printf(&s->display, "+ +\r\n"); in malta_fgpa_display_event()
567 qemu_chr_fe_printf(&s->display, "+--------+\r\n"); in malta_fgpa_display_event()
568 s->display_inited = true; in malta_fgpa_display_event()
580 memory_region_init_io(&s->iomem, NULL, &malta_fpga_ops, s, in malta_fpga_init()
581 "malta-fpga", 0x100000); in malta_fpga_init()
582 memory_region_init_alias(&s->iomem_lo, NULL, "malta-fpga", in malta_fpga_init()
583 &s->iomem, 0, 0x900); in malta_fpga_init()
584 memory_region_init_alias(&s->iomem_hi, NULL, "malta-fpga", in malta_fpga_init()
585 &s->iomem, 0xa00, 0x100000 - 0xa00); in malta_fpga_init()
587 memory_region_add_subregion(address_space, base, &s->iomem_lo); in malta_fpga_init()
588 memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi); in malta_fpga_init()
590 chr = qemu_chr_new("fpga", "vc:320x200", NULL); in malta_fpga_init()
591 qemu_chr_fe_init(&s->display, chr, NULL); in malta_fpga_init()
592 qemu_chr_fe_set_handlers(&s->display, NULL, NULL, in malta_fpga_init()
595 s->uart = serial_mm_init(address_space, base + 0x900, 3, uart_irq, in malta_fpga_init()
626 /* setup MEM-to-PCI0 mapping as done by YAMON */ in bl_setup_gt64120_jump_kernel()
633 /* setup PCI0 io window to 0x18000000-0x181fffff */ in bl_setup_gt64120_jump_kernel()
658 * The PIIX ISA bridge is on PCI bus 0 dev 10 func 0. in bl_setup_gt64120_jump_kernel()
672 true, ENVP_VADDR - 64, in bl_setup_gt64120_jump_kernel()
722 * environment variables tables. Those tables contain the 32-bit address
731 * a0 - number of kernel arguments
732 * a1 - 32-bit address of the kernel arguments table
733 * a2 - 32-bit address of the environment variables table
734 * a3 - RAM size in bytes
770 * - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff in write_bootloader()
771 * - set up PCI0 MEM0 at 0x10000000, size 0x7e00000 in write_bootloader()
772 * - set up PCI0 MEM1 at 0x18200000, size 0xbc00000 in write_bootloader()
805 stl_p(p++, 0x258cffff); /* addiu t4,t4,-1 */ in write_bootloader()
856 memcpy(opaque, hex->str, hex->len); in reinitialize_rng_seed()
885 error_report("Trap-and-Emul kernels (Linux CONFIG_KVM_GUEST)" in load_kernel()
902 - (initrd_size + 128 * KiB), in load_kernel()
911 loaderparams.ram_size - initrd_offset); in load_kernel()
913 if (initrd_size == (target_ulong) -1) { in load_kernel()
948 prom_set(prom_buf, prom_index++, "%s", hex->str); in load_kernel()
964 unsigned int smp_cpus = ms->smp.cpus; in malta_mips_config()
965 CPUMIPSState *env = &cpu->env; in malta_mips_config()
969 env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0, in malta_mips_config()
971 smp_cpus * cs->nr_threads - 1); in malta_mips_config()
972 env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0, in malta_mips_config()
973 CP0MVPC0_PVPE, 4, smp_cpus - 1); in malta_mips_config()
981 slot = PCI_SLOT(pci_dev->devfn); in malta_pci_slot_get_pirq()
995 return ((slot - 18) + irq_num) & 0x03; in malta_pci_slot_get_pirq()
1005 CPUMIPSState *env = &cpu->env; in main_cpu_reset()
1015 env->CP0_Status &= ~(1 << CP0St_ERL); in main_cpu_reset()
1028 for (i = 0; i < ms->smp.cpus; i++) { in create_cpu_without_cps()
1029 cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk, in create_cpu_without_cps()
1039 env = &cpu->env; in create_cpu_without_cps()
1040 *i8259_irq = env->irq[2]; in create_cpu_without_cps()
1041 *cbus_irq = env->irq[4]; in create_cpu_without_cps()
1047 object_initialize_child(OBJECT(s), "cps", &s->cps, TYPE_MIPS_CPS); in create_cps()
1048 object_property_set_str(OBJECT(&s->cps), "cpu-type", ms->cpu_type, in create_cps()
1050 object_property_set_bool(OBJECT(&s->cps), "cpu-big-endian", in create_cps()
1052 object_property_set_uint(OBJECT(&s->cps), "num-vp", ms->smp.cpus, in create_cps()
1054 qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk); in create_cps()
1055 sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); in create_cps()
1057 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); in create_cps()
1059 *i8259_irq = get_cps_irq(&s->cps, 3); in create_cps()
1066 if ((ms->smp.cpus > 1) && cpu_type_supports_cps_smp(ms->cpu_type)) { in mips_create_cpu()
1076 ram_addr_t ram_size = machine->ram_size; in mips_malta_init()
1078 const char *kernel_filename = machine->kernel_filename; in mips_malta_init()
1079 const char *kernel_cmdline = machine->kernel_cmdline; in mips_malta_init()
1080 const char *initrd_filename = machine->initrd_filename; in mips_malta_init()
1114 memory_region_add_subregion(system_memory, 0x80000000, machine->ram); in mips_malta_init()
1118 machine->ram, 0, MIN(ram_size, 256 * MiB)); in mips_malta_init()
1126 machine->ram, 512 * MiB, in mips_malta_init()
1127 ram_size - 512 * MiB); in mips_malta_init()
1132 /* FPGA */ in mips_malta_init()
1159 if (!cpu_type_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) { in mips_malta_init()
1175 machine->firmware ?: bios_name); in mips_malta_init()
1181 bios_size = -1; in mips_malta_init()
1184 machine->firmware && !qtest_enabled()) { in mips_malta_init()
1185 error_report("Could not load MIPS bios '%s'", machine->firmware); in mips_malta_init()
1191 * a neat trick which allows bi-endian firmware. in mips_malta_init()
1229 qdev_prop_set_bit(dev, "cpu-little-endian", !TARGET_BIG_ENDIAN); in mips_malta_init()
1268 s->cpuclk = qdev_init_clock_out(DEVICE(obj), "cpu-refclk"); in mips_malta_instance_init()
1269 clock_set_hz(s->cpuclk, 320000000); /* 320 MHz */ in mips_malta_instance_init()
1280 { "PIIX4_PM", "memory-hotplug-support", "off" },
1281 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" },
1282 { "PIIX4_PM", "acpi-root-pci-hotplug", "off" },
1283 { "PIIX4_PM", "x-not-migrate-acpi-index", "true" },
1289 mc->desc = "MIPS Malta Core LV"; in mips_malta_machine_init()
1290 mc->init = mips_malta_init; in mips_malta_machine_init()
1291 mc->block_default_type = IF_IDE; in mips_malta_machine_init()
1292 mc->max_cpus = 16; in mips_malta_machine_init()
1293 mc->is_default = true; in mips_malta_machine_init()
1295 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("20Kc"); in mips_malta_machine_init()
1297 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf"); in mips_malta_machine_init()
1299 mc->default_ram_id = "mips_malta.ram"; in mips_malta_machine_init()
1300 compat_props_add(mc->compat_props, malta_compat, malta_compat_len); in mips_malta_machine_init()