52 static qemu_irq xive_tctx_output(XiveTCTX *tctx, uint8_t ring)  in xive_tctx_output()  argument
58                 return tctx->os_output;  in xive_tctx_output()
61                 return tctx->hv_output;  in xive_tctx_output()
67 static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring)  in xive_tctx_accept()  argument
69     uint8_t *regs = &tctx->regs[ring];  in xive_tctx_accept()
73     qemu_irq_lower(xive_tctx_output(tctx, ring));  in xive_tctx_accept()
87         trace_xive_tctx_accept(tctx->cs->cpu_index, ring,  in xive_tctx_accept()
95 static void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring)  in xive_tctx_notify()  argument
97     uint8_t *regs = &tctx->regs[ring];  in xive_tctx_notify()
110         trace_xive_tctx_notify(tctx->cs->cpu_index, ring,  in xive_tctx_notify()
113         qemu_irq_raise(xive_tctx_output(tctx, ring));  in xive_tctx_notify()
117 void xive_tctx_reset_os_signal(XiveTCTX *tctx)  in xive_tctx_reset_os_signal()  argument
125     qemu_irq_lower(xive_tctx_output(tctx, TM_QW1_OS));  in xive_tctx_reset_os_signal()
128 static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr)  in xive_tctx_set_cppr()  argument
130     uint8_t *regs = &tctx->regs[ring];  in xive_tctx_set_cppr()
132     trace_xive_tctx_set_cppr(tctx->cs->cpu_index, ring,  in xive_tctx_set_cppr()
140     tctx->regs[ring + TM_CPPR] = cppr;  in xive_tctx_set_cppr()
143     xive_tctx_notify(tctx, ring);  in xive_tctx_set_cppr()
146 void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb)  in xive_tctx_ipb_update()  argument
148     uint8_t *regs = &tctx->regs[ring];  in xive_tctx_ipb_update()
152     xive_tctx_notify(tctx, ring);  in xive_tctx_ipb_update()
159 static void xive_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx,  in xive_tm_set_hv_cppr()  argument
162     xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff);  in xive_tm_set_hv_cppr()
165 static uint64_t xive_tm_ack_hv_reg(XivePresenter *xptr, XiveTCTX *tctx,  in xive_tm_ack_hv_reg()  argument
168     return xive_tctx_accept(tctx, TM_QW3_HV_PHYS);  in xive_tm_ack_hv_reg()
171 static uint64_t xive_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx,  in xive_tm_pull_pool_ctx()  argument
174     uint32_t qw2w2_prev = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]);  in xive_tm_pull_pool_ctx()
178     memcpy(&tctx->regs[TM_QW2_HV_POOL + TM_WORD2], &qw2w2, 4);  in xive_tm_pull_pool_ctx()
182 static void xive_tm_vt_push(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,  in xive_tm_vt_push()  argument
185     tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff;  in xive_tm_vt_push()
188 static uint64_t xive_tm_vt_poll(XivePresenter *xptr, XiveTCTX *tctx,  in xive_tm_vt_poll()  argument
191     return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff;  in xive_tm_vt_poll()
266 static void xive_tm_raw_write(XiveTCTX *tctx, hwaddr offset, uint64_t value,  in xive_tm_raw_write()  argument
291             tctx->regs[reg_offset + i] = (value >> (8 * (size - i - 1))) &  in xive_tm_raw_write()
297 static uint64_t xive_tm_raw_read(XiveTCTX *tctx, hwaddr offset, unsigned size)  in xive_tm_raw_read()  argument
318         ret |= (uint64_t) tctx->regs[reg_offset + i] << (8 * (size - i - 1));  in xive_tm_raw_read()
332 static uint64_t xive_tm_ack_os_reg(XivePresenter *xptr, XiveTCTX *tctx,  in xive_tm_ack_os_reg()  argument
335     return xive_tctx_accept(tctx, TM_QW1_OS);  in xive_tm_ack_os_reg()
338 static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx,  in xive_tm_set_os_cppr()  argument
341     xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff);  in xive_tm_set_os_cppr()
348 static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx,  in xive_tm_set_os_pending()  argument
351     xive_tctx_ipb_update(tctx, TM_QW1_OS, xive_priority_to_ipb(value & 0xff));  in xive_tm_set_os_pending()
368 static uint32_t xive_tctx_get_os_cam(XiveTCTX *tctx, uint8_t *nvt_blk,  in xive_tctx_get_os_cam()  argument
371     uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);  in xive_tctx_get_os_cam()
378 static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t qw1w2)  in xive_tctx_set_os_cam()  argument
380     memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);  in xive_tctx_set_os_cam()
383 static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,  in xive_tm_pull_os_ctx()  argument
392     qw1w2 = xive_tctx_get_os_cam(tctx, &nvt_blk, &nvt_idx, &vo);  in xive_tm_pull_os_ctx()
401     xive_tctx_set_os_cam(tctx, qw1w2_new);  in xive_tm_pull_os_ctx()
403     xive_tctx_reset_os_signal(tctx);  in xive_tm_pull_os_ctx()
407 static void xive_tctx_need_resend(XiveRouter *xrtr, XiveTCTX *tctx,  in xive_tctx_need_resend()  argument
438     xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb);  in xive_tctx_need_resend()
444 static void xive_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,  in xive_tm_push_os_ctx()  argument
456     xive_tctx_set_os_cam(tctx, qw1w2);  in xive_tm_push_os_ctx()
460         xive_tctx_need_resend(XIVE_ROUTER(xptr), tctx, nvt_blk, nvt_idx);  in xive_tm_push_os_ctx()
479     void     (*write_handler)(XivePresenter *xptr, XiveTCTX *tctx,
482     uint64_t (*read_handler)(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
563 void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,  in xive_tctx_tm_write()  argument
568     trace_xive_tctx_tm_write(tctx->cs->cpu_index, offset, size, value);  in xive_tctx_tm_write()
578         xto = xive_tm_find_op(tctx->xptr, offset, size, true);  in xive_tctx_tm_write()
583             xto->write_handler(xptr, tctx, offset, value, size);  in xive_tctx_tm_write()
591     xto = xive_tm_find_op(tctx->xptr, offset, size, true);  in xive_tctx_tm_write()
593         xto->write_handler(xptr, tctx, offset, value, size);  in xive_tctx_tm_write()
600     xive_tm_raw_write(tctx, offset, value, size);  in xive_tctx_tm_write()
603 uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,  in xive_tctx_tm_read()  argument
617         xto = xive_tm_find_op(tctx->xptr, offset, size, false);  in xive_tctx_tm_read()
623         ret = xto->read_handler(xptr, tctx, offset, size);  in xive_tctx_tm_read()
630     xto = xive_tm_find_op(tctx->xptr, offset, size, false);  in xive_tctx_tm_read()
632         ret = xto->read_handler(xptr, tctx, offset, size);  in xive_tctx_tm_read()
639     ret = xive_tm_raw_read(tctx, offset, size);  in xive_tctx_tm_read()
641     trace_xive_tctx_tm_read(tctx->cs->cpu_index, offset, size, ret);  in xive_tctx_tm_read()
671 void xive_tctx_pic_print_info(XiveTCTX *tctx, GString *buf)  in xive_tctx_pic_print_info()  argument
679     if (!tctx) {  in xive_tctx_pic_print_info()
683     cpu_index = tctx->cs ? tctx->cs->cpu_index : -1;  in xive_tctx_pic_print_info()
685     if (xive_in_kernel(tctx->xptr)) {  in xive_tctx_pic_print_info()
688         kvmppc_xive_cpu_synchronize_state(tctx, &local_err);  in xive_tctx_pic_print_info()
695     if (xive_presenter_get_config(tctx->xptr) & XIVE_PRESENTER_GEN1_TIMA_OS) {  in xive_tctx_pic_print_info()
706         char *s = xive_tctx_ring_print(&tctx->regs[i * XIVE_TM_RING_SIZE]);  in xive_tctx_pic_print_info()
713 void xive_tctx_reset(XiveTCTX *tctx)  in xive_tctx_reset()  argument
715     memset(tctx->regs, 0, sizeof(tctx->regs));  in xive_tctx_reset()
718     tctx->regs[TM_QW1_OS + TM_LSMFB] = 0xFF;  in xive_tctx_reset()
719     tctx->regs[TM_QW1_OS + TM_ACK_CNT] = 0xFF;  in xive_tctx_reset()
720     tctx->regs[TM_QW1_OS + TM_AGE] = 0xFF;  in xive_tctx_reset()
726     tctx->regs[TM_QW1_OS + TM_PIPR] =  in xive_tctx_reset()
727         ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]);  in xive_tctx_reset()
728     tctx->regs[TM_QW3_HV_PHYS + TM_PIPR] =  in xive_tctx_reset()
729         ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]);  in xive_tctx_reset()
734     XiveTCTX *tctx = XIVE_TCTX(dev);  in xive_tctx_realize()  local
738     assert(tctx->cs);  in xive_tctx_realize()
739     assert(tctx->xptr);  in xive_tctx_realize()
741     cpu = POWERPC_CPU(tctx->cs);  in xive_tctx_realize()
745         tctx->hv_output = qdev_get_gpio_in(DEVICE(cpu), POWER9_INPUT_HINT);  in xive_tctx_realize()
746         tctx->os_output = qdev_get_gpio_in(DEVICE(cpu), POWER9_INPUT_INT);  in xive_tctx_realize()
756     if (xive_in_kernel(tctx->xptr)) {  in xive_tctx_realize()
757         if (kvmppc_xive_cpu_connect(tctx, errp) < 0) {  in xive_tctx_realize()
765     XiveTCTX *tctx = XIVE_TCTX(opaque);  in vmstate_xive_tctx_pre_save()  local
769     if (xive_in_kernel(tctx->xptr)) {  in vmstate_xive_tctx_pre_save()
770         ret = kvmppc_xive_cpu_get_state(tctx, &local_err);  in vmstate_xive_tctx_pre_save()
782     XiveTCTX *tctx = XIVE_TCTX(opaque);  in vmstate_xive_tctx_post_load()  local
786     if (xive_in_kernel(tctx->xptr)) {  in vmstate_xive_tctx_post_load()
791         ret = kvmppc_xive_cpu_set_state(tctx, &local_err);  in vmstate_xive_tctx_post_load()
858 void xive_tctx_destroy(XiveTCTX *tctx)  in xive_tctx_destroy()  argument
860     Object *obj = OBJECT(tctx);  in xive_tctx_destroy()
1537 static uint32_t xive_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx)  in xive_tctx_hw_cam_line()  argument
1539     CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env;  in xive_tctx_hw_cam_line()
1549 int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,  in xive_presenter_tctx_match()  argument
1555     uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]);  in xive_presenter_tctx_match()
1556     uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]);  in xive_presenter_tctx_match()
1557     uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);  in xive_presenter_tctx_match()
1558     uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]);  in xive_presenter_tctx_match()
1580             cam == xive_tctx_hw_cam_line(xptr, tctx)) {  in xive_presenter_tctx_match()
1630     XiveTCTXMatch match = { .tctx = NULL, .ring = 0 };  in xive_presenter_notify()
1645         xive_tctx_ipb_update(match.tctx, match.ring,  in xive_presenter_notify()