Lines Matching +full:ls +full:- +full:bits
4 * Copyright (c) 2017-2018, IBM Corporation.
6 * SPDX-License-Identifier: GPL-2.0-or-later
17 #include "hw/qdev-properties.h"
34 if (!(tctx->regs[cur_ring + TM_WORD2] & 0x80)) { in xive_ring_valid()
87 return tctx->os_output; in xive_tctx_output()
90 return tctx->hv_output; in xive_tctx_output()
102 uint8_t *sig_regs = &tctx->regs[sig_ring]; in xive_tctx_accept()
107 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_NSR] == 0); in xive_tctx_accept()
108 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_PIPR] == 0); in xive_tctx_accept()
109 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_CPPR] == 0); in xive_tctx_accept()
117 regs = &tctx->regs[ring]; in xive_tctx_accept()
133 trace_xive_tctx_accept(tctx->cs->cpu_index, ring, in xive_tctx_accept()
146 uint8_t *regs = &tctx->regs[ring]; in xive_tctx_pipr_set()
166 trace_xive_tctx_notify(tctx->cs->cpu_index, ring, in xive_tctx_pipr_set()
181 * should be raised again when re-pushing the lower privilege context. in xive_tctx_reset_signal()
188 uint8_t *sig_regs = &tctx->regs[ring]; in xive_tctx_set_cppr()
194 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_NSR] == 0); in xive_tctx_set_cppr()
195 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_PIPR] == 0); in xive_tctx_set_cppr()
196 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_CPPR] == 0); in xive_tctx_set_cppr()
199 trace_xive_tctx_set_cppr(tctx->cs->cpu_index, ring, in xive_tctx_set_cppr()
218 uint8_t *pool_regs = &tctx->regs[TM_QW2_HV_POOL]; in xive_tctx_set_cppr()
242 uint8_t *regs = &tctx->regs[ring]; in xive_tctx_pipr_recompute_from_ipb()
254 uint8_t *regs = &tctx->regs[ring]; in xive_tctx_pipr_present()
302 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); in xive_tctx_get_pool_cam()
311 memcpy(&tctx->regs[TM_QW2_HV_POOL + TM_WORD2], &qw2w2, 4); in xive_tctx_set_pool_cam()
336 /* Re-check phys for interrupts if pool was disabled */ in xive_tm_pull_pool_ctx()
345 uint8_t qw3b8 = tctx->regs[TM_QW3_HV_PHYS + TM_WORD2]; in xive_tm_pull_phys_ctx()
348 qw3b8 = tctx->regs[TM_QW3_HV_PHYS + TM_WORD2]; in xive_tm_pull_phys_ctx()
353 tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = qw3b8_new; in xive_tm_pull_phys_ctx()
363 tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff; in xive_tm_vt_push()
369 return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff; in xive_tm_vt_poll()
377 * Registers accessibility bits :
379 * 0x0 - no access
380 * 0x1 - write only
381 * 0x2 - read only
382 * 0x3 - read/write
386 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */
387 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 3, /* QW-1 OS */
388 0, 0, 3, 3, 0, 3, 3, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */
389 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 3, 3, 3, 0, /* QW-3 PHYS */
393 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */
394 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 3, /* QW-1 OS */
395 0, 0, 3, 3, 0, 3, 3, 0, 0, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */
396 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 0, 0, 0, 0, /* QW-3 PHYS */
400 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */
401 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */
402 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */
403 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */
407 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-0 User */
408 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */
409 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */
410 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */
437 mask |= (uint64_t) 0xff << (8 * (size - i - 1)); in xive_tm_mask()
467 uint8_t byte_mask = (mask >> (8 * (size - i - 1))); in xive_tm_raw_write()
469 tctx->regs[reg_offset + i] = (value >> (8 * (size - i - 1))) & in xive_tm_raw_write()
490 return -1; in xive_tm_raw_read()
496 ret |= (uint64_t) tctx->regs[reg_offset + i] << (8 * (size - i - 1)); in xive_tm_raw_read()
524 uint8_t *regs = &tctx->regs[ring]; in xive_tctx_set_lgs()
549 uint8_t *regs = &tctx->regs[ring]; in xive_tm_set_os_pending()
573 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); in xive_tctx_get_os_cam()
582 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); in xive_tctx_set_os_cam()
616 * Grab the associated NVT to pull the pending bits, and merge in xive_tctx_restore_nvp()
632 uint8_t *regs = &tctx->regs[TM_QW1_OS]; in xive_tctx_restore_nvp()
654 /* Check the interrupt pending bits */ in xive_tm_push_os_ctx()
674 return xpc->get_config(xptr); in xive_presenter_get_config()
810 if (xto->page_offset >= page_offset && in xive_tm_find_op()
811 xto->op_offset == op_offset && in xive_tm_find_op()
812 xto->size == size && in xive_tm_find_op()
813 ((write && xto->write_handler) || (!write && xto->read_handler))) { in xive_tm_find_op()
831 trace_xive_tctx_tm_write(tctx->cs->cpu_index, offset, size, value); in xive_tctx_tm_write()
836 xto = xive_tm_find_op(tctx->xptr, offset, size, true); in xive_tctx_tm_write()
838 if (hw_owned && !xto->hw_ok) { in xive_tctx_tm_write()
842 if (!hw_owned && !xto->sw_ok) { in xive_tctx_tm_write()
853 xto->write_handler(xptr, tctx, offset, value, size); in xive_tctx_tm_write()
862 xto->write_handler(xptr, tctx, offset, value, size); in xive_tctx_tm_write()
886 xto = xive_tm_find_op(tctx->xptr, offset, size, false); in xive_tctx_tm_read()
888 if (hw_owned && !xto->hw_ok) { in xive_tctx_tm_read()
892 if (!hw_owned && !xto->sw_ok) { in xive_tctx_tm_read()
905 return -1; in xive_tctx_tm_read()
907 ret = xto->read_handler(xptr, tctx, offset, size); in xive_tctx_tm_read()
915 ret = xto->read_handler(xptr, tctx, offset, size); in xive_tctx_tm_read()
924 trace_xive_tctx_tm_read(tctx->cs->cpu_index, offset, size, ret); in xive_tctx_tm_read()
951 xpc->in_kernel ? xpc->in_kernel(xptr) : false; \
966 cpu_index = tctx->cs ? tctx->cs->cpu_index : -1; in xive_tctx_pic_print_info()
968 if (xive_in_kernel(tctx->xptr)) { in xive_tctx_pic_print_info()
978 if (xive_presenter_get_config(tctx->xptr) & XIVE_PRESENTER_GEN1_TIMA_OS) { in xive_tctx_pic_print_info()
984 "QW NSR CPPR IPB LSMFB - LGS T PIPR" in xive_tctx_pic_print_info()
989 char *s = xive_tctx_ring_print(&tctx->regs[i * XIVE_TM_RING_SIZE]); in xive_tctx_pic_print_info()
998 memset(tctx->regs, 0, sizeof(tctx->regs)); in xive_tctx_reset()
1001 tctx->regs[TM_QW1_OS + TM_LSMFB] = 0xFF; in xive_tctx_reset()
1002 tctx->regs[TM_QW1_OS + TM_ACK_CNT] = 0xFF; in xive_tctx_reset()
1003 tctx->regs[TM_QW1_OS + TM_AGE] = 0xFF; in xive_tctx_reset()
1004 if (!(xive_presenter_get_config(tctx->xptr) & in xive_tctx_reset()
1006 tctx->regs[TM_QW1_OS + TM_OGEN] = 2; in xive_tctx_reset()
1013 tctx->regs[TM_QW1_OS + TM_PIPR] = in xive_tctx_reset()
1014 xive_ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]); in xive_tctx_reset()
1015 tctx->regs[TM_QW3_HV_PHYS + TM_PIPR] = in xive_tctx_reset()
1016 xive_ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]); in xive_tctx_reset()
1025 assert(tctx->cs); in xive_tctx_realize()
1026 assert(tctx->xptr); in xive_tctx_realize()
1028 cpu = POWERPC_CPU(tctx->cs); in xive_tctx_realize()
1029 env = &cpu->env; in xive_tctx_realize()
1032 tctx->hv_output = qdev_get_gpio_in(DEVICE(cpu), POWER9_INPUT_HINT); in xive_tctx_realize()
1033 tctx->os_output = qdev_get_gpio_in(DEVICE(cpu), POWER9_INPUT_INT); in xive_tctx_realize()
1043 if (xive_in_kernel(tctx->xptr)) { in xive_tctx_realize()
1056 if (xive_in_kernel(tctx->xptr)) { in vmstate_xive_tctx_pre_save()
1073 if (xive_in_kernel(tctx->xptr)) { in vmstate_xive_tctx_post_load()
1110 dc->desc = "XIVE Interrupt Thread Context"; in xive_tctx_class_init()
1111 dc->realize = xive_tctx_realize; in xive_tctx_class_init()
1112 dc->vmsd = &vmstate_xive_tctx; in xive_tctx_class_init()
1118 dc->user_creatable = false; in xive_tctx_class_init()
1211 assert(srcno < xsrc->nr_irqs); in xive_source_esb_get()
1213 return xsrc->status[srcno] & 0x3; in xive_source_esb_get()
1218 assert(srcno < xsrc->nr_irqs); in xive_source_esb_set()
1220 return xive_esb_set(&xsrc->status[srcno], pq); in xive_source_esb_set()
1243 * on the PQ state bits of MSIs is disabled
1247 return (xsrc->esb_flags & XIVE_SRC_PQ_DISABLE) && in xive_source_esb_disabled()
1258 assert(srcno < xsrc->nr_irqs); in xive_source_esb_trigger()
1264 ret = xive_esb_trigger(&xsrc->status[srcno]); in xive_source_esb_trigger()
1282 assert(srcno < xsrc->nr_irqs); in xive_source_esb_eoi()
1289 ret = xive_esb_eoi(&xsrc->status[srcno]); in xive_source_esb_eoi()
1309 XiveNotifierClass *xnc = XIVE_NOTIFIER_GET_CLASS(xsrc->xive); in xive_source_notify()
1312 if (xnc->notify) { in xive_source_notify()
1313 xnc->notify(xsrc->xive, srcno, pq_checked); in xive_source_notify()
1329 addr_is_even(addr, xsrc->esb_shift - 1); in xive_source_is_trigger_page()
1338 * 0x000 .. 0x3FF -1 EOI and return 0|1
1339 * 0x400 .. 0x7FF -1 EOI and return 0|1
1340 * 0x800 .. 0xBFF -1 return PQ
1341 * 0xC00 .. 0xCFF -1 return PQ and atomically PQ=00
1342 * 0xD00 .. 0xDFF -1 return PQ and atomically PQ=01
1343 * 0xE00 .. 0xDFF -1 return PQ and atomically PQ=10
1344 * 0xF00 .. 0xDFF -1 return PQ and atomically PQ=11
1350 uint32_t srcno = addr >> xsrc->esb_shift; in xive_source_esb_read()
1351 uint64_t ret = -1; in xive_source_esb_read()
1358 return -1; in xive_source_esb_read()
1411 uint32_t srcno = addr >> xsrc->esb_shift; in xive_source_esb_write()
1428 if (!(xsrc->esb_flags & XIVE_SRC_STORE_EOI)) { in xive_source_esb_write()
1439 * state bits are not controlled locally. Such as for LSIs when in xive_source_esb_write()
1507 for (unsigned i = 0; i < xsrc->nr_irqs; i++) { in xive_source_pic_print_info()
1516 pq & XIVE_ESB_VAL_P ? 'P' : '-', in xive_source_pic_print_info()
1517 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', in xive_source_pic_print_info()
1528 memset(xsrc->status, xsrc->reset_pq, xsrc->nr_irqs); in xive_source_reset()
1536 assert(xsrc->xive); in xive_source_realize()
1538 if (!xsrc->nr_irqs) { in xive_source_realize()
1543 if (xsrc->esb_shift != XIVE_ESB_4K && in xive_source_realize()
1544 xsrc->esb_shift != XIVE_ESB_4K_2PAGE && in xive_source_realize()
1545 xsrc->esb_shift != XIVE_ESB_64K && in xive_source_realize()
1546 xsrc->esb_shift != XIVE_ESB_64K_2PAGE) { in xive_source_realize()
1551 xsrc->status = g_malloc0(xsrc->nr_irqs); in xive_source_realize()
1552 xsrc->lsi_map = bitmap_new(xsrc->nr_irqs); in xive_source_realize()
1554 memory_region_init(&xsrc->esb_mmio, OBJECT(xsrc), "xive.esb", esb_len); in xive_source_realize()
1555 memory_region_init_io(&xsrc->esb_mmio_emulated, OBJECT(xsrc), in xive_source_realize()
1556 &xive_source_esb_ops, xsrc, "xive.esb-emulated", in xive_source_realize()
1558 memory_region_add_subregion(&xsrc->esb_mmio, 0, &xsrc->esb_mmio_emulated); in xive_source_realize()
1580 DEFINE_PROP_UINT32("nr-irqs", XiveSource, nr_irqs, 0),
1586 DEFINE_PROP_UINT8("reset-pq", XiveSource, reset_pq, XIVE_ESB_OFF),
1595 dc->desc = "XIVE Interrupt Source"; in xive_source_class_init()
1597 dc->realize = xive_source_realize; in xive_source_class_init()
1598 dc->vmsd = &vmstate_xive_source; in xive_source_class_init()
1603 dc->user_creatable = false; in xive_source_class_init()
1620 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); in xive_end_queue_pic_print_info()
1621 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); in xive_end_queue_pic_print_info()
1626 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window in xive_end_queue_pic_print_info()
1629 qindex = (qindex - (width - 1)) & (qentries - 1); in xive_end_queue_pic_print_info()
1632 uint32_t qdata = -1; in xive_end_queue_pic_print_info()
1640 g_string_append_printf(buf, "%s%08x ", i == width - 1 ? "^" : "", in xive_end_queue_pic_print_info()
1642 qindex = (qindex + 1) & (qentries - 1); in xive_end_queue_pic_print_info()
1650 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); in xive_end_pic_print_info()
1651 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); in xive_end_pic_print_info()
1652 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); in xive_end_pic_print_info()
1655 uint32_t nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); in xive_end_pic_print_info()
1656 uint32_t nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); in xive_end_pic_print_info()
1657 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); in xive_end_pic_print_info()
1664 pq = xive_get_field32(END_W1_ESn, end->w1); in xive_end_pic_print_info()
1669 pq & XIVE_ESB_VAL_P ? 'P' : '-', in xive_end_pic_print_info()
1670 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', in xive_end_pic_print_info()
1671 xive_end_is_valid(end) ? 'v' : '-', in xive_end_pic_print_info()
1672 xive_end_is_enqueue(end) ? 'q' : '-', in xive_end_pic_print_info()
1673 xive_end_is_notify(end) ? 'n' : '-', in xive_end_pic_print_info()
1674 xive_end_is_backlog(end) ? 'b' : '-', in xive_end_pic_print_info()
1675 xive_end_is_escalate(end) ? 'e' : '-', in xive_end_pic_print_info()
1676 xive_end_is_uncond_escalation(end) ? 'u' : '-', in xive_end_pic_print_info()
1677 xive_end_is_silent_escalation(end) ? 's' : '-', in xive_end_pic_print_info()
1678 xive_end_is_firmware(end) ? 'f' : '-', in xive_end_pic_print_info()
1692 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); in xive_end_enqueue()
1693 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); in xive_end_enqueue()
1694 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); in xive_end_enqueue()
1707 qindex = (qindex + 1) & (qentries - 1); in xive_end_enqueue()
1710 end->w1 = xive_set_field32(END_W1_GENERATION, end->w1, qgen); in xive_end_enqueue()
1712 end->w1 = xive_set_field32(END_W1_PAGE_OFF, end->w1, qindex); in xive_end_enqueue()
1717 XiveEAS *eas = (XiveEAS *) &end->w4; in xive_end_eas_pic_print_info()
1724 pq = xive_get_field32(END_W1_ESe, end->w1); in xive_end_eas_pic_print_info()
1728 pq & XIVE_ESB_VAL_P ? 'P' : '-', in xive_end_eas_pic_print_info()
1729 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', in xive_end_eas_pic_print_info()
1732 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), in xive_end_eas_pic_print_info()
1733 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), in xive_end_eas_pic_print_info()
1734 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); in xive_end_eas_pic_print_info()
1746 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); in xive_router_get_eas()
1755 return xrc->get_pq(xrtr, eas_blk, eas_idx, pq); in xive_router_get_pq()
1764 return xrc->set_pq(xrtr, eas_blk, eas_idx, pq); in xive_router_set_pq()
1772 return xrc->get_end(xrtr, end_blk, end_idx, end); in xive_router_get_end()
1780 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); in xive_router_write_end()
1788 return xrc->get_nvt(xrtr, nvt_blk, nvt_idx, nvt); in xive_router_get_nvt()
1796 return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number); in xive_router_write_nvt()
1803 return xrc->get_block_id(xrtr); in xive_router_get_block_id()
1810 assert(xrtr->xfb); in xive_router_realize()
1817 return xrc->end_notify(xrtr, eas); in xive_router_end_notify_handler()
1827 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; in xive_tctx_hw_cam_line()
1828 uint32_t pir = env->spr_cb[SPR_PIR].default_value; in xive_tctx_hw_cam_line()
1838 * (starting with the least significant bits) in the NVP index in xive_get_vpgroup_size()
1897 /* Crowd level bits reside in upper 2 bits of the 6 bit group level */ in xive_get_group_level()
1904 * The thread context register words are in big-endian format.
1912 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); in xive_presenter_tctx_match()
1913 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); in xive_presenter_tctx_match()
1914 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); in xive_presenter_tctx_match()
1915 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); in xive_presenter_tctx_match()
1918 * TODO (PowerNV): ignore mode. The low order bits of the NVT in xive_presenter_tctx_match()
1925 * F=0 & i=1: Logical server notification (bits ignored at in xive_presenter_tctx_match()
1928 qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n", in xive_presenter_tctx_match()
1930 return -1; in xive_presenter_tctx_match()
1953 /* F=1 : User level Event-Based Branch (EBB) notification */ in xive_presenter_tctx_match()
1963 return -1; in xive_presenter_tctx_match()
1982 * For VP-specific notification, we expect at most one match and in xive_presenter_match()
1986 * For VP-group notification, match_nvt() is the equivalent of the in xive_presenter_match()
2002 return xfc->match_nvt(xfb, format, nvt_blk, nvt_idx, crowd, cam_ignore, in xive_presenter_match()
2015 uint8_t pq = xive_get_field32(end_esmask, end->w1); in xive_router_end_es_notify()
2018 if (pq != xive_get_field32(end_esmask, end->w1)) { in xive_router_end_es_notify()
2019 end->w1 = xive_set_field32(end_esmask, end->w1, pq); in xive_router_end_es_notify()
2042 uint8_t end_blk = xive_get_field64(EAS_END_BLOCK, eas->w); in xive_router_end_notify()
2043 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); in xive_router_end_notify()
2044 uint32_t end_data = xive_get_field64(EAS_END_DATA, eas->w); in xive_router_end_notify()
2078 * F=1 : User level Event-Based Branch (EBB) notification, no in xive_router_end_notify()
2121 /* we don't support VP-group notification on P9, so precluded is not used */ in xive_router_end_notify()
2122 if (xive_presenter_match(xrtr->xfb, format, nvt_blk, nvt_idx, in xive_router_end_notify()
2135 * - specific VP: update the NVT structure if backlog is activated in xive_router_end_notify()
2136 * - logical server : forward request to IVPE (not supported) in xive_router_end_notify()
2164 * If activated, escalate notification using the ESe PQ bits and in xive_router_end_notify()
2165 * the EAS in w4-5 in xive_router_end_notify()
2245 DEFINE_PROP_LINK("xive-fabric", XiveRouter, xfb,
2255 dc->desc = "XIVE Router Engine"; in xive_router_class_init()
2258 dc->realize = xive_router_realize; in xive_router_class_init()
2259 xnc->notify = xive_router_notify; in xive_router_class_init()
2262 xrc->end_notify = xive_router_end_notify; in xive_router_class_init()
2287 (uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w), in xive_eas_pic_print_info()
2288 (uint32_t) xive_get_field64(EAS_END_INDEX, eas->w), in xive_eas_pic_print_info()
2289 (uint32_t) xive_get_field64(EAS_END_DATA, eas->w)); in xive_eas_pic_print_info()
2304 uint64_t ret = -1; in xive_end_source_read()
2310 end_blk = xive_router_get_block_id(xsrc->xrtr); in xive_end_source_read()
2311 end_idx = addr >> (xsrc->esb_shift + 1); in xive_end_source_read()
2315 if (xive_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { in xive_end_source_read()
2318 return -1; in xive_end_source_read()
2324 return -1; in xive_end_source_read()
2327 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END_W1_ESn : END_W1_ESe; in xive_end_source_read()
2350 return -1; in xive_end_source_read()
2355 xive_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); in xive_end_source_read()
2389 assert(xsrc->xrtr); in xive_end_source_realize()
2391 if (!xsrc->nr_ends) { in xive_end_source_realize()
2396 if (xsrc->esb_shift != XIVE_ESB_4K && in xive_end_source_realize()
2397 xsrc->esb_shift != XIVE_ESB_64K) { in xive_end_source_realize()
2406 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), in xive_end_source_realize()
2408 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); in xive_end_source_realize()
2412 DEFINE_PROP_UINT32("nr-ends", XiveENDSource, nr_ends, 0),
2422 dc->desc = "XIVE END Source"; in xive_end_source_class_init()
2424 dc->realize = xive_end_source_realize; in xive_end_source_class_init()
2429 dc->user_creatable = false; in xive_end_source_class_init()