33 #include "hw/qdev-properties.h"
34 #include "qemu/error-report.h"
38 #include "hw/intc/intc.h"
55     cpu_index = icp->cs ? icp->cs->cpu_index : -1;  in icp_pic_print_info()
57     if (!icp->output) {  in icp_pic_print_info()
66                            cpu_index, icp->xirr, icp->xirr_owner,  in icp_pic_print_info()
67                            icp->pending_priority, icp->mfrr);  in icp_pic_print_info()
75                            ics->offset, ics->offset + ics->nr_irqs - 1, ics);  in ics_pic_print_info()
77     if (!ics->irqs) {  in ics_pic_print_info()
85     for (i = 0; i < ics->nr_irqs; i++) {  in ics_pic_print_info()
86         ICSIRQState *irq = ics->irqs + i;  in ics_pic_print_info()
88         if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) {  in ics_pic_print_info()
92                                ics->offset + i,  in ics_pic_print_info()
93                                (irq->flags & XICS_FLAGS_IRQ_LSI) ?  in ics_pic_print_info()
95                                irq->priority, irq->status);  in ics_pic_print_info()
106 #define XISR(icp)   (((icp)->xirr) & XISR_MASK)
107 #define CPPR(icp)   (((icp)->xirr) >> 24)
109 static void ics_reject(ICSState *ics, uint32_t nr);
110 static void ics_eoi(ICSState *ics, uint32_t nr);
114     if (XISR(icp) && (icp->pending_priority <= icp->mfrr)) {  in icp_check_ipi()
118     trace_xics_icp_check_ipi(icp->cs->cpu_index, icp->mfrr);  in icp_check_ipi()
120     if (XISR(icp) && icp->xirr_owner) {  in icp_check_ipi()
121         ics_reject(icp->xirr_owner, XISR(icp));  in icp_check_ipi()
124     icp->xirr = (icp->xirr & ~XISR_MASK) | XICS_IPI;  in icp_check_ipi()
125     icp->pending_priority = icp->mfrr;  in icp_check_ipi()
126     icp->xirr_owner = NULL;  in icp_check_ipi()
127     qemu_irq_raise(icp->output);  in icp_check_ipi()
132     XICSFabric *xi = icp->xics;  in icp_resend()
135     if (icp->mfrr < CPPR(icp)) {  in icp_resend()
139     xic->ics_resend(xi);  in icp_resend()
148     icp->xirr = (icp->xirr & ~CPPR_MASK) | (cppr << 24);  in icp_set_cppr()
151         if (XISR(icp) && (cppr <= icp->pending_priority)) {  in icp_set_cppr()
153             icp->xirr &= ~XISR_MASK; /* Clear XISR */  in icp_set_cppr()
154             icp->pending_priority = 0xff;  in icp_set_cppr()
155             qemu_irq_lower(icp->output);  in icp_set_cppr()
156             if (icp->xirr_owner) {  in icp_set_cppr()
157                 ics_reject(icp->xirr_owner, old_xisr);  in icp_set_cppr()
158                 icp->xirr_owner = NULL;  in icp_set_cppr()
170     icp->mfrr = mfrr;  in icp_set_mfrr()
178     uint32_t xirr = icp->xirr;  in icp_accept()
180     qemu_irq_lower(icp->output);  in icp_accept()
181     icp->xirr = icp->pending_priority << 24;  in icp_accept()
182     icp->pending_priority = 0xff;  in icp_accept()
183     icp->xirr_owner = NULL;  in icp_accept()
185     trace_xics_icp_accept(xirr, icp->xirr);  in icp_accept()
193         *mfrr = icp->mfrr;  in icp_ipoll()
195     return icp->xirr;  in icp_ipoll()
200     XICSFabric *xi = icp->xics;  in icp_eoi()
205     /* Send EOI -> ICS */  in icp_eoi()
206     icp->xirr = (icp->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);  in icp_eoi()
207     trace_xics_icp_eoi(icp->cs->cpu_index, xirr, icp->xirr);  in icp_eoi()
210     ics = xic->ics_get(xi, irq);  in icp_eoi()
219 void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)  in icp_irq()  argument
221     ICPState *icp = xics_icp_get(ics->xics, server);  in icp_irq()
223     trace_xics_icp_irq(server, nr, priority);  in icp_irq()
226         || (XISR(icp) && (icp->pending_priority <= priority))) {  in icp_irq()
227         ics_reject(ics, nr);  in icp_irq()
229         if (XISR(icp) && icp->xirr_owner) {  in icp_irq()
230             ics_reject(icp->xirr_owner, XISR(icp));  in icp_irq()
231             icp->xirr_owner = NULL;  in icp_irq()
233         icp->xirr = (icp->xirr & ~XISR_MASK) | (nr & XISR_MASK);  in icp_irq()
234         icp->xirr_owner = ics;  in icp_irq()
235         icp->pending_priority = priority;  in icp_irq()
236         trace_xics_icp_raise(icp->xirr, icp->pending_priority);  in icp_irq()
237         qemu_irq_raise(icp->output);  in icp_irq()
287     icp->xirr = 0;  in icp_reset()
288     icp->pending_priority = 0xff;  in icp_reset()
289     icp->mfrr = 0xff;  in icp_reset()
308     assert(icp->xics);  in icp_realize()
309     assert(icp->cs);  in icp_realize()
311     cpu = POWERPC_CPU(icp->cs);  in icp_realize()
312     env = &cpu->env;  in icp_realize()
315         icp->output = qdev_get_gpio_in(DEVICE(cpu), POWER7_INPUT_INT);  in icp_realize()
318         icp->output = qdev_get_gpio_in(DEVICE(cpu), POWER9_INPUT_INT);  in icp_realize()
322         icp->output = qdev_get_gpio_in(DEVICE(cpu), PPC970_INPUT_INT);  in icp_realize()
358     dc->realize = icp_realize;  in icp_class_init()
359     dc->unrealize = icp_unrealize;  in icp_class_init()
365     dc->user_creatable = false;  in icp_class_init()
405     ICSIRQState *irq = ics->irqs + srcno;  in ics_resend_msi()
408     if (irq->status & XICS_STATUS_REJECTED) {  in ics_resend_msi()
409         irq->status &= ~XICS_STATUS_REJECTED;  in ics_resend_msi()
410         if (irq->priority != 0xff) {  in ics_resend_msi()
411             icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);  in ics_resend_msi()
418     ICSIRQState *irq = ics->irqs + srcno;  in ics_resend_lsi()
420     if ((irq->priority != 0xff)  in ics_resend_lsi()
421         && (irq->status & XICS_STATUS_ASSERTED)  in ics_resend_lsi()
422         && !(irq->status & XICS_STATUS_SENT)) {  in ics_resend_lsi()
423         irq->status |= XICS_STATUS_SENT;  in ics_resend_lsi()
424         icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);  in ics_resend_lsi()
430     ICSIRQState *irq = ics->irqs + srcno;  in ics_set_irq_msi()
432     trace_xics_ics_set_irq_msi(srcno, srcno + ics->offset);  in ics_set_irq_msi()
435         if (irq->priority == 0xff) {  in ics_set_irq_msi()
436             irq->status |= XICS_STATUS_MASKED_PENDING;  in ics_set_irq_msi()
439             icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);  in ics_set_irq_msi()
446     ICSIRQState *irq = ics->irqs + srcno;  in ics_set_irq_lsi()
448     trace_xics_ics_set_irq_lsi(srcno, srcno + ics->offset);  in ics_set_irq_lsi()
450         irq->status |= XICS_STATUS_ASSERTED;  in ics_set_irq_lsi()
452         irq->status &= ~XICS_STATUS_ASSERTED;  in ics_set_irq_lsi()
466     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {  in ics_set_irq()
475     ICSIRQState *irq = ics->irqs + srcno;  in ics_write_xive_msi()
477     if (!(irq->status & XICS_STATUS_MASKED_PENDING)  in ics_write_xive_msi()
478         || (irq->priority == 0xff)) {  in ics_write_xive_msi()
482     irq->status &= ~XICS_STATUS_MASKED_PENDING;  in ics_write_xive_msi()
483     icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);  in ics_write_xive_msi()
494     ICSIRQState *irq = ics->irqs + srcno;  in ics_write_xive()
496     irq->server = server;  in ics_write_xive()
497     irq->priority = priority;  in ics_write_xive()
498     irq->saved_priority = saved_priority;  in ics_write_xive()
500     trace_xics_ics_write_xive(ics->offset + srcno, srcno, server, priority);  in ics_write_xive()
502     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {  in ics_write_xive()
509 static void ics_reject(ICSState *ics, uint32_t nr)  in ics_reject()  argument
512     ICSIRQState *irq = ics->irqs + nr - ics->offset;  in ics_reject()
514     if (isc->reject) {  in ics_reject()
515         isc->reject(ics, nr);  in ics_reject()
519     trace_xics_ics_reject(nr, nr - ics->offset);  in ics_reject()
520     if (irq->flags & XICS_FLAGS_IRQ_MSI) {  in ics_reject()
521         irq->status |= XICS_STATUS_REJECTED;  in ics_reject()
522     } else if (irq->flags & XICS_FLAGS_IRQ_LSI) {  in ics_reject()
523         irq->status &= ~XICS_STATUS_SENT;  in ics_reject()
532     if (isc->resend) {  in ics_resend()
533         isc->resend(ics);  in ics_resend()
537     for (i = 0; i < ics->nr_irqs; i++) {  in ics_resend()
539         if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {  in ics_resend()
547 static void ics_eoi(ICSState *ics, uint32_t nr)  in ics_eoi()  argument
549     int srcno = nr - ics->offset;  in ics_eoi()
550     ICSIRQState *irq = ics->irqs + srcno;  in ics_eoi()
552     trace_xics_ics_eoi(nr);  in ics_eoi()
554     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {  in ics_eoi()
555         irq->status &= ~XICS_STATUS_SENT;  in ics_eoi()
561     irq->priority = 0xff;  in ics_reset_irq()
562     irq->saved_priority = 0xff;  in ics_reset_irq()
568     g_autofree uint8_t *flags = g_malloc(ics->nr_irqs);  in ics_reset_hold()
571     for (i = 0; i < ics->nr_irqs; i++) {  in ics_reset_hold()
572         flags[i] = ics->irqs[i].flags;  in ics_reset_hold()
575     memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);  in ics_reset_hold()
577     for (i = 0; i < ics->nr_irqs; i++) {  in ics_reset_hold()
578         ics_reset_irq(ics->irqs + i);  in ics_reset_hold()
579         ics->irqs[i].flags = flags[i];  in ics_reset_hold()
601     assert(ics->xics);  in ics_realize()
603     if (!ics->nr_irqs) {  in ics_realize()
607     ics->irqs = g_new0(ICSIRQState, ics->nr_irqs);  in ics_realize()
616     ics->offset = XICS_IRQ_BASE;  in ics_instance_init()
672         VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs,
680     DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0),
691     dc->realize = ics_realize;  in ics_class_init()
693     dc->vmsd = &vmstate_ics;  in ics_class_init()
698     dc->user_creatable = false;  in ics_class_init()
699     rc->phases.hold = ics_reset_hold;  in ics_class_init()
724     return xic->icp_get(xi, server);  in xics_icp_get()
729     assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK));  in ics_set_irq_type()
731     ics->irqs[srcno].flags |=  in ics_set_irq_type()
737         ics_reset_irq(ics->irqs + srcno);  in ics_set_irq_type()