Lines Matching +full:intc +full:- +full:nr +full:- +full:irqs
4 * Copyright (c) 2017-2018, IBM Corporation.
7 * COPYING file in the top-level directory.
14 #include "qemu/error-report.h"
25 #include "hw/qdev-properties.h"
52 return nvt_idx - SPAPR_XIVE_NVT_BASE; in spapr_xive_nvt_to_target()
65 *out_nvt_idx = SPAPR_XIVE_NVT_BASE + cpu->vcpu_id; in spapr_xive_cpu_to_nvt()
75 return -1; in spapr_xive_target_to_nvt()
112 *out_end_idx = (cpu->vcpu_id << 3) + prio; in spapr_xive_cpu_to_end()
122 return -1; in spapr_xive_target_to_end()
137 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); in spapr_xive_end_pic_print_info()
138 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); in spapr_xive_end_pic_print_info()
139 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); in spapr_xive_end_pic_print_info()
141 uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6); in spapr_xive_end_pic_print_info()
142 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); in spapr_xive_end_pic_print_info()
156 (kvm_irqchip_in_kernel() && (xive)->fd != -1)
160 XiveSource *xsrc = &xive->source; in spapr_xive_pic_print_info()
175 for (i = 0; i < xive->nr_irqs; i++) { in spapr_xive_pic_print_info()
177 XiveEAS *eas = &xive->eat[i]; in spapr_xive_pic_print_info()
185 pq & XIVE_ESB_VAL_P ? 'P' : '-', in spapr_xive_pic_print_info()
186 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', in spapr_xive_pic_print_info()
189 (int) xive_get_field64(EAS_END_DATA, eas->w)); in spapr_xive_pic_print_info()
192 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); in spapr_xive_pic_print_info()
195 assert(end_idx < xive->nr_ends); in spapr_xive_pic_print_info()
196 end = &xive->endt[end_idx]; in spapr_xive_pic_print_info()
209 memory_region_set_enabled(&xive->source.esb_mmio, enable); in spapr_xive_mmio_set_enabled()
210 memory_region_set_enabled(&xive->tm_mmio, enable); in spapr_xive_mmio_set_enabled()
213 memory_region_set_enabled(&xive->end_source.esb_mmio, false); in spapr_xive_mmio_set_enabled()
219 XiveTCTX *tctx = spapr_cpu_state(POWERPC_CPU(current_cpu))->tctx; in spapr_xive_tm_write()
226 XiveTCTX *tctx = spapr_cpu_state(POWERPC_CPU(current_cpu))->tctx; in spapr_xive_tm_read()
250 end->w1 = cpu_to_be32(END_W1_ESe_Q | END_W1_ESn_Q); in spapr_xive_end_reset()
260 * IRQs (!P|Q) in spapr_xive_reset()
264 for (i = 0; i < xive->nr_irqs; i++) { in spapr_xive_reset()
265 XiveEAS *eas = &xive->eat[i]; in spapr_xive_reset()
267 eas->w = cpu_to_be64(EAS_VALID | EAS_MASKED); in spapr_xive_reset()
269 eas->w = 0; in spapr_xive_reset()
274 for (i = 0; i < xive->nr_ends; i++) { in spapr_xive_reset()
275 spapr_xive_end_reset(&xive->endt[i]); in spapr_xive_reset()
283 object_initialize_child(obj, "source", &xive->source, TYPE_XIVE_SOURCE); in spapr_xive_instance_init()
285 object_initialize_child(obj, "end_source", &xive->end_source, in spapr_xive_instance_init()
289 xive->fd = -1; in spapr_xive_instance_init()
296 XiveSource *xsrc = &xive->source; in spapr_xive_realize()
297 XiveENDSource *end_xsrc = &xive->end_source; in spapr_xive_realize()
301 g_assert(xive->nr_irqs); in spapr_xive_realize()
302 g_assert(xive->nr_ends); in spapr_xive_realize()
304 sxc->parent_realize(dev, &local_err); in spapr_xive_realize()
313 object_property_set_int(OBJECT(xsrc), "nr-irqs", xive->nr_irqs, in spapr_xive_realize()
323 object_property_set_int(OBJECT(end_xsrc), "nr-ends", xive->nr_irqs, in spapr_xive_realize()
332 xive->end_base = xive->vc_base + xive_source_esb_len(xsrc); in spapr_xive_realize()
337 xive->eat = g_new0(XiveEAS, xive->nr_irqs); in spapr_xive_realize()
338 xive->endt = g_new0(XiveEND, xive->nr_ends); in spapr_xive_realize()
340 xive->nodename = g_strdup_printf("interrupt-controller@%" PRIx64, in spapr_xive_realize()
341 xive->tm_base + XIVE_TM_USER_PAGE * (1 << TM_SHIFT)); in spapr_xive_realize()
346 memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &spapr_xive_tm_ops, in spapr_xive_realize()
353 memory_region_add_subregion(get_system_memory(), xive->vc_base, in spapr_xive_realize()
354 &xsrc->esb_mmio); in spapr_xive_realize()
355 memory_region_add_subregion(get_system_memory(), xive->end_base, in spapr_xive_realize()
356 &end_xsrc->esb_mmio); in spapr_xive_realize()
357 memory_region_add_subregion(get_system_memory(), xive->tm_base, in spapr_xive_realize()
358 &xive->tm_mmio); in spapr_xive_realize()
366 if (eas_idx >= xive->nr_irqs) { in spapr_xive_get_eas()
367 return -1; in spapr_xive_get_eas()
370 *eas = xive->eat[eas_idx]; in spapr_xive_get_eas()
379 if (end_idx >= xive->nr_ends) { in spapr_xive_get_end()
380 return -1; in spapr_xive_get_end()
383 memcpy(end, &xive->endt[end_idx], sizeof(XiveEND)); in spapr_xive_get_end()
393 if (end_idx >= xive->nr_ends) { in spapr_xive_write_end()
394 return -1; in spapr_xive_write_end()
397 memcpy(&xive->endt[end_idx], end, sizeof(XiveEND)); in spapr_xive_write_end()
409 return -1; in spapr_xive_get_nvt()
416 nvt->w0 = cpu_to_be32(NVT_W0_VALID); in spapr_xive_get_nvt()
426 * machine should never hit a non-scheduled NVT. It should never in spapr_xive_write_nvt()
442 XiveTCTX *tctx = spapr_cpu_state(cpu)->tctx; in spapr_xive_match_nvt()
462 if (ring != -1) { in spapr_xive_match_nvt()
463 if (match->tctx) { in spapr_xive_match_nvt()
466 return -1; in spapr_xive_match_nvt()
469 match->ring = ring; in spapr_xive_match_nvt()
470 match->tctx = tctx; in spapr_xive_match_nvt()
505 *pq = xive_source_esb_get(&xive->source, idx); in spapr_xive_get_pq()
516 *pq = xive_source_esb_set(&xive->source, idx, *pq); in spapr_xive_set_pq()
563 static int spapr_xive_post_load(SpaprInterruptController *intc, int version_id) in spapr_xive_post_load() argument
565 SpaprXive *xive = SPAPR_XIVE(intc); in spapr_xive_post_load()
590 static int spapr_xive_claim_irq(SpaprInterruptController *intc, int lisn, in spapr_xive_claim_irq() argument
593 SpaprXive *xive = SPAPR_XIVE(intc); in spapr_xive_claim_irq()
594 XiveSource *xsrc = &xive->source; in spapr_xive_claim_irq()
596 assert(lisn < xive->nr_irqs); in spapr_xive_claim_irq()
600 if (xive_eas_is_valid(&xive->eat[lisn])) { in spapr_xive_claim_irq()
602 return -EBUSY; in spapr_xive_claim_irq()
608 xive->eat[lisn].w |= cpu_to_be64(EAS_VALID | EAS_MASKED); in spapr_xive_claim_irq()
620 static void spapr_xive_free_irq(SpaprInterruptController *intc, int lisn) in spapr_xive_free_irq() argument
622 SpaprXive *xive = SPAPR_XIVE(intc); in spapr_xive_free_irq()
623 assert(lisn < xive->nr_irqs); in spapr_xive_free_irq()
627 xive->eat[lisn].w &= cpu_to_be64(~EAS_VALID); in spapr_xive_free_irq()
631 DEFINE_PROP_UINT32("nr-irqs", SpaprXive, nr_irqs, 0),
632 DEFINE_PROP_UINT32("nr-ends", SpaprXive, nr_ends, 0),
633 DEFINE_PROP_UINT64("vc-base", SpaprXive, vc_base, SPAPR_XIVE_VC_BASE),
634 DEFINE_PROP_UINT64("tm-base", SpaprXive, tm_base, SPAPR_XIVE_TM_BASE),
635 DEFINE_PROP_UINT8("hv-prio", SpaprXive, hv_prio, 7),
639 static int spapr_xive_cpu_intc_create(SpaprInterruptController *intc, in spapr_xive_cpu_intc_create() argument
642 SpaprXive *xive = SPAPR_XIVE(intc); in spapr_xive_cpu_intc_create()
648 return -1; in spapr_xive_cpu_intc_create()
651 spapr_cpu->tctx = XIVE_TCTX(obj); in spapr_xive_cpu_intc_create()
658 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); in xive_tctx_set_os_cam()
661 static void spapr_xive_cpu_intc_reset(SpaprInterruptController *intc, in spapr_xive_cpu_intc_reset() argument
664 XiveTCTX *tctx = spapr_cpu_state(cpu)->tctx; in spapr_xive_cpu_intc_reset()
680 static void spapr_xive_cpu_intc_destroy(SpaprInterruptController *intc, in spapr_xive_cpu_intc_destroy() argument
685 xive_tctx_destroy(spapr_cpu->tctx); in spapr_xive_cpu_intc_destroy()
686 spapr_cpu->tctx = NULL; in spapr_xive_cpu_intc_destroy()
689 static void spapr_xive_set_irq(SpaprInterruptController *intc, int irq, int val) in spapr_xive_set_irq() argument
691 SpaprXive *xive = SPAPR_XIVE(intc); in spapr_xive_set_irq()
696 kvmppc_xive_source_set_irq(&xive->source, irq, val); in spapr_xive_set_irq()
698 xive_source_set_irq(&xive->source, irq, val); in spapr_xive_set_irq()
702 static void spapr_xive_print_info(SpaprInterruptController *intc, GString *buf) in spapr_xive_print_info() argument
704 SpaprXive *xive = SPAPR_XIVE(intc); in spapr_xive_print_info()
710 xive_tctx_pic_print_info(spapr_cpu_state(cpu)->tctx, buf); in spapr_xive_print_info()
715 static void spapr_xive_dt(SpaprInterruptController *intc, uint32_t nr_servers, in spapr_xive_dt() argument
718 SpaprXive *xive = SPAPR_XIVE(intc); in spapr_xive_dt()
727 * EQ size - the sizes of pages supported by the system 4K, 64K, in spapr_xive_dt()
739 cpu_to_be32(xive->hv_prio), /* start */ in spapr_xive_dt()
740 cpu_to_be32(0xff - xive->hv_prio), /* count */ in spapr_xive_dt()
744 timas[0] = cpu_to_be64(xive->tm_base + in spapr_xive_dt()
747 timas[2] = cpu_to_be64(xive->tm_base + in spapr_xive_dt()
751 _FDT(node = fdt_add_subnode(fdt, 0, xive->nodename)); in spapr_xive_dt()
753 _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe")); in spapr_xive_dt()
756 _FDT(fdt_setprop_string(fdt, node, "compatible", "ibm,power-ivpe")); in spapr_xive_dt()
757 _FDT(fdt_setprop(fdt, node, "ibm,xive-eq-sizes", eq_sizes, in spapr_xive_dt()
759 _FDT(fdt_setprop(fdt, node, "ibm,xive-lisn-ranges", lisn_ranges, in spapr_xive_dt()
763 _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0)); in spapr_xive_dt()
764 _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); in spapr_xive_dt()
771 * The "ibm,plat-res-int-priorities" property defines the priority in spapr_xive_dt()
774 _FDT(fdt_setprop(fdt, 0, "ibm,plat-res-int-priorities", in spapr_xive_dt()
778 static int spapr_xive_activate(SpaprInterruptController *intc, in spapr_xive_activate() argument
781 SpaprXive *xive = SPAPR_XIVE(intc); in spapr_xive_activate()
784 int rc = spapr_irq_init_kvm(kvmppc_xive_connect, intc, nr_servers, in spapr_xive_activate()
797 static void spapr_xive_deactivate(SpaprInterruptController *intc) in spapr_xive_deactivate() argument
799 SpaprXive *xive = SPAPR_XIVE(intc); in spapr_xive_deactivate()
804 kvmppc_xive_disconnect(intc); in spapr_xive_deactivate()
821 dc->desc = "sPAPR XIVE Interrupt Controller"; in spapr_xive_class_init()
824 &sxc->parent_realize); in spapr_xive_class_init()
825 dc->vmsd = &vmstate_spapr_xive; in spapr_xive_class_init()
827 xrc->get_eas = spapr_xive_get_eas; in spapr_xive_class_init()
828 xrc->get_pq = spapr_xive_get_pq; in spapr_xive_class_init()
829 xrc->set_pq = spapr_xive_set_pq; in spapr_xive_class_init()
830 xrc->get_end = spapr_xive_get_end; in spapr_xive_class_init()
831 xrc->write_end = spapr_xive_write_end; in spapr_xive_class_init()
832 xrc->get_nvt = spapr_xive_get_nvt; in spapr_xive_class_init()
833 xrc->write_nvt = spapr_xive_write_nvt; in spapr_xive_class_init()
834 xrc->get_block_id = spapr_xive_get_block_id; in spapr_xive_class_init()
836 sicc->activate = spapr_xive_activate; in spapr_xive_class_init()
837 sicc->deactivate = spapr_xive_deactivate; in spapr_xive_class_init()
838 sicc->cpu_intc_create = spapr_xive_cpu_intc_create; in spapr_xive_class_init()
839 sicc->cpu_intc_reset = spapr_xive_cpu_intc_reset; in spapr_xive_class_init()
840 sicc->cpu_intc_destroy = spapr_xive_cpu_intc_destroy; in spapr_xive_class_init()
841 sicc->claim_irq = spapr_xive_claim_irq; in spapr_xive_class_init()
842 sicc->free_irq = spapr_xive_free_irq; in spapr_xive_class_init()
843 sicc->set_irq = spapr_xive_set_irq; in spapr_xive_class_init()
844 sicc->print_info = spapr_xive_print_info; in spapr_xive_class_init()
845 sicc->dt = spapr_xive_dt; in spapr_xive_class_init()
846 sicc->post_load = spapr_xive_post_load; in spapr_xive_class_init()
848 xpc->match_nvt = spapr_xive_match_nvt; in spapr_xive_class_init()
849 xpc->get_config = spapr_xive_presenter_get_config; in spapr_xive_class_init()
850 xpc->in_kernel = spapr_xive_in_kernel_xptr; in spapr_xive_class_init()
895 return priority >= xive->hv_prio; in type_init()
905 * - R4: "flags"
906 * Bits 0-63 reserved
907 * - R5: "lisn" is per "interrupts", "interrupt-map", or
908 * "ibm,xive-lisn-ranges" properties, or as returned by the
909 * ibm,query-interrupt-source-number RTAS call, or as returned
913 * - R4: "flags"
914 * Bits 0-59: Reserved
920 * - R5: Logical Real address of full function Event State Buffer
921 * management page, -1 if H_INT_ESB hcall flag is set to 1.
922 * - R6: Logical Real Address of trigger only Event State Buffer
923 * management page or -1.
924 * - R7: Power of 2 page size for the ESB management pages returned in
939 SpaprXive *xive = spapr->xive; in h_int_get_source_info()
940 XiveSource *xsrc = &xive->source; in h_int_get_source_info()
946 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { in h_int_get_source_info()
954 if (lisn >= xive->nr_irqs) { in h_int_get_source_info()
960 if (!xive_eas_is_valid(&xive->eat[lisn])) { in h_int_get_source_info()
974 if (xsrc->esb_flags & XIVE_SRC_STORE_EOI) { in h_int_get_source_info()
980 * interrupt. This is necessary under KVM to re-trigger the in h_int_get_source_info()
988 args[1] = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn); in h_int_get_source_info()
990 args[1] = -1; in h_int_get_source_info()
995 args[2] = xive->vc_base + xive_source_esb_page(xsrc, lisn); in h_int_get_source_info()
997 args[2] = -1; in h_int_get_source_info()
1001 args[3] = xsrc->esb_shift - 1; in h_int_get_source_info()
1003 args[3] = xsrc->esb_shift; in h_int_get_source_info()
1018 * - R4: "flags"
1019 * Bits 0-61: Reserved
1024 * set. There is no race-free way of unmasking and restoring the
1029 * - R5: "lisn" is per "interrupts", "interrupt-map", or
1030 * "ibm,xive-lisn-ranges" properties, or as returned by the
1031 * ibm,query-interrupt-source-number RTAS call, or as returned by
1033 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or
1034 * "ibm,ppc-interrupt-gserver#s"
1035 * - R7: "priority" is a valid priority not in
1036 * "ibm,plat-res-int-priorities"
1037 * - R8: "eisn" is the guest EISN associated with the "lisn"
1040 * - None
1051 SpaprXive *xive = spapr->xive; in h_int_set_source_config()
1063 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { in h_int_set_source_config()
1071 if (lisn >= xive->nr_irqs) { in h_int_set_source_config()
1077 eas = xive->eat[lisn]; in h_int_set_source_config()
1129 xive->eat[lisn] = new_eas; in h_int_set_source_config()
1140 * - R4: "flags"
1141 * Bits 0-63 Reserved
1142 * - R5: "lisn" is per "interrupts", "interrupt-map", or
1143 * "ibm,xive-lisn-ranges" properties, or as returned by the
1144 * ibm,query-interrupt-source-number RTAS call, or as
1148 * - R4: Target to which the specified Logical Interrupt Source is
1150 * - R5: Priority to which the specified Logical Interrupt Source is
1152 * - R6: EISN for the specified Logical Interrupt Source (this will be
1160 SpaprXive *xive = spapr->xive; in h_int_get_source_config()
1170 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { in h_int_get_source_config()
1178 if (lisn >= xive->nr_irqs) { in h_int_get_source_config()
1184 eas = xive->eat[lisn]; in h_int_get_source_config()
1194 assert(end_idx < xive->nr_ends); in h_int_get_source_config()
1195 end = &xive->endt[end_idx]; in h_int_get_source_config()
1197 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); in h_int_get_source_config()
1198 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); in h_int_get_source_config()
1204 args[1] = xive_get_field32(END_W7_F0_PRIORITY, end->w7); in h_int_get_source_config()
1219 * - R4: "flags"
1220 * Bits 0-63 Reserved
1221 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1222 * "ibm,ppc-interrupt-gserver#s"
1223 * - R6: "priority" is a valid priority not in
1224 * "ibm,plat-res-int-priorities"
1227 * - R4: Logical real address of notification page
1228 * - R5: Power of 2 page size of the notification page
1235 SpaprXive *xive = spapr->xive; in h_int_get_queue_info()
1236 XiveENDSource *end_xsrc = &xive->end_source; in h_int_get_queue_info()
1246 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { in h_int_get_queue_info()
1274 assert(end_idx < xive->nr_ends); in h_int_get_queue_info()
1275 end = &xive->endt[end_idx]; in h_int_get_queue_info()
1277 args[0] = xive->end_base + (1ull << (end_xsrc->esb_shift + 1)) * end_idx; in h_int_get_queue_info()
1279 args[1] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; in h_int_get_queue_info()
1302 * - R4: "flags"
1303 * Bits 0-62: Reserved
1305 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1306 * "ibm,ppc-interrupt-gserver#s"
1307 * - R6: "priority" is a valid priority not in
1308 * "ibm,plat-res-int-priorities"
1309 * - R7: "eventQueue": The logical real address of the start of the EQ
1310 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes"
1313 * - None
1323 SpaprXive *xive = spapr->xive; in h_int_set_queue_config()
1335 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { in h_int_set_queue_config()
1364 assert(end_idx < xive->nr_ends); in h_int_set_queue_config()
1365 memcpy(&end, &xive->endt[end_idx], sizeof(XiveEND)); in h_int_set_queue_config()
1381 end.w0 = xive_set_field32(END_W0_QSIZE, end.w0, qsize - 12); in h_int_set_queue_config()
1402 eq = address_space_map(CPU(cpu)->as, qpage, &plen, true, in h_int_set_queue_config()
1409 address_space_unmap(CPU(cpu)->as, eq, plen, true, plen); in h_int_set_queue_config()
1440 * TODO: issue syncs required to ensure all in-flight interrupts in h_int_set_queue_config()
1456 memcpy(&xive->endt[end_idx], &end, sizeof(XiveEND)); in h_int_set_queue_config()
1466 * - R4: "flags"
1467 * Bits 0-62: Reserved
1469 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1470 * "ibm,ppc-interrupt-gserver#s"
1471 * - R6: "priority" is a valid priority not in
1472 * "ibm,plat-res-int-priorities"
1475 * - R4: "flags":
1476 * Bits 0-61: Reserved
1480 * - R5: The logical real address of the start of the EQ
1481 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes"
1482 * - R7: The value of Event Queue Offset Counter per XIVE spec
1494 SpaprXive *xive = spapr->xive; in h_int_get_queue_config()
1504 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { in h_int_get_queue_config()
1532 assert(end_idx < xive->nr_ends); in h_int_get_queue_config()
1533 end = &xive->endt[end_idx]; in h_int_get_queue_config()
1542 args[2] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; in h_int_get_queue_config()
1561 args[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION, end->w1) << 62; in h_int_get_queue_config()
1564 args[3] = xive_get_field32(END_W1_PAGE_OFF, end->w1); in h_int_get_queue_config()
1577 * interrupt. The reporting cache lines can be reset by inputting -1
1584 * - R4: "flags"
1585 * Bits 0-63: Reserved
1586 * - R5: "reportingLine": The logical real address of the reporting cache
1590 * - None
1601 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { in h_int_set_os_reporting_line()
1617 * "target". If no reporting cache line pair has been set, -1 is
1622 * - R4: "flags"
1623 * Bits 0-63: Reserved
1624 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1625 * "ibm,ppc-interrupt-gserver#s"
1626 * - R6: "reportingLine": The logical real address of the reporting
1630 * - R4: The logical real address of the reporting line if set, else -1
1641 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { in h_int_get_os_reporting_line()
1662 * - R4: "flags"
1663 * Bits 0-62: Reserved
1665 * - R5: "lisn" is per "interrupts", "interrupt-map", or
1666 * "ibm,xive-lisn-ranges" properties, or as returned by the
1667 * ibm,query-interrupt-source-number RTAS call, or as
1669 * - R6: "esbOffset" is the offset into the ESB page for the load or
1671 * - R7: "storeData" is the data to write for a store operation
1674 * - R4: The value of the load if load operation, else -1
1684 SpaprXive *xive = spapr->xive; in h_int_esb()
1691 XiveSource *xsrc = &xive->source; in h_int_esb()
1695 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { in h_int_esb()
1703 if (lisn >= xive->nr_irqs) { in h_int_esb()
1709 eas = xive->eat[lisn]; in h_int_esb()
1716 if (offset > (1ull << xsrc->esb_shift)) { in h_int_esb()
1724 mmio_addr = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn) + offset; in h_int_esb()
1733 args[0] = (flags & SPAPR_XIVE_ESB_STORE) ? -1 : data; in h_int_esb()
1745 * - R4: "flags"
1746 * Bits 0-63: Reserved
1747 * - R5: "lisn" is per "interrupts", "interrupt-map", or
1748 * "ibm,xive-lisn-ranges" properties, or as returned by the
1749 * ibm,query-interrupt-source-number RTAS call, or as
1753 * - None
1760 SpaprXive *xive = spapr->xive; in h_int_sync()
1767 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { in h_int_sync()
1775 if (lisn >= xive->nr_irqs) { in h_int_sync()
1781 eas = xive->eat[lisn]; in h_int_sync()
1818 * - R4: "flags"
1819 * Bits 0-63: Reserved
1822 * - None
1829 SpaprXive *xive = spapr->xive; in h_int_reset()
1834 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { in h_int_reset()