49 static uint32_t riscv_imsic_topei(RISCVIMSICState *imsic, uint32_t page)  in riscv_imsic_topei()  argument
53     base = page * imsic->num_irqs;  in riscv_imsic_topei()
54     max_irq = (imsic->eithreshold[page] &&  in riscv_imsic_topei()
55                (imsic->eithreshold[page] <= imsic->num_irqs)) ?  in riscv_imsic_topei()
56                imsic->eithreshold[page] : imsic->num_irqs;  in riscv_imsic_topei()
58         if ((imsic->eistate[base + i] & IMSIC_EISTATE_ENPEND) ==  in riscv_imsic_topei()
67 static void riscv_imsic_update(RISCVIMSICState *imsic, uint32_t page)  in riscv_imsic_update()  argument
69     if (imsic->eidelivery[page] && riscv_imsic_topei(imsic, page)) {  in riscv_imsic_update()
70         qemu_irq_raise(imsic->external_irqs[page]);  in riscv_imsic_update()
72         qemu_irq_lower(imsic->external_irqs[page]);  in riscv_imsic_update()
76 static int riscv_imsic_eidelivery_rmw(RISCVIMSICState *imsic, uint32_t page,  in riscv_imsic_eidelivery_rmw()  argument
81     target_ulong old_val = imsic->eidelivery[page];  in riscv_imsic_eidelivery_rmw()
88     imsic->eidelivery[page] = (old_val & ~wr_mask) | (new_val & wr_mask);  in riscv_imsic_eidelivery_rmw()
90     riscv_imsic_update(imsic, page);  in riscv_imsic_eidelivery_rmw()
94 static int riscv_imsic_eithreshold_rmw(RISCVIMSICState *imsic, uint32_t page,  in riscv_imsic_eithreshold_rmw()  argument
99     target_ulong old_val = imsic->eithreshold[page];  in riscv_imsic_eithreshold_rmw()
106     imsic->eithreshold[page] = (old_val & ~wr_mask) | (new_val & wr_mask);  in riscv_imsic_eithreshold_rmw()
108     riscv_imsic_update(imsic, page);  in riscv_imsic_eithreshold_rmw()
112 static int riscv_imsic_topei_rmw(RISCVIMSICState *imsic, uint32_t page,  in riscv_imsic_topei_rmw()  argument
116     uint32_t base, topei = riscv_imsic_topei(imsic, page);  in riscv_imsic_topei_rmw()
126         base = page * imsic->num_irqs;  in riscv_imsic_topei_rmw()
128             imsic->eistate[base + topei] &= ~IMSIC_EISTATE_PENDING;  in riscv_imsic_topei_rmw()
131         riscv_imsic_update(imsic, page);  in riscv_imsic_topei_rmw()
137 static int riscv_imsic_eix_rmw(RISCVIMSICState *imsic,  in riscv_imsic_eix_rmw()  argument
152     if (num >= (imsic->num_irqs / xlen)) {  in riscv_imsic_eix_rmw()
156     base = (page * imsic->num_irqs) + (num * xlen);  in riscv_imsic_eix_rmw()
162             *val |= (imsic->eistate[base + i] & state) ? mask : 0;  in riscv_imsic_eix_rmw()
175                 imsic->eistate[base + i] |= state;  in riscv_imsic_eix_rmw()
177                 imsic->eistate[base + i] &= ~state;  in riscv_imsic_eix_rmw()
182     riscv_imsic_update(imsic, page);  in riscv_imsic_eix_rmw()
189     RISCVIMSICState *imsic = arg;  in riscv_imsic_rmw()  local
198     if (imsic->mmode) {  in riscv_imsic_rmw()
207                 if (vgein && vgein < imsic->num_pages) {  in riscv_imsic_rmw()
222         return riscv_imsic_eidelivery_rmw(imsic, page, val,  in riscv_imsic_rmw()
225         return riscv_imsic_eithreshold_rmw(imsic, page, val,  in riscv_imsic_rmw()
228         return riscv_imsic_topei_rmw(imsic, page, val, new_val, wr_mask);  in riscv_imsic_rmw()
230         return riscv_imsic_eix_rmw(imsic, xlen, page,  in riscv_imsic_rmw()
234         return riscv_imsic_eix_rmw(imsic, xlen, page,  in riscv_imsic_rmw()
250     RISCVIMSICState *imsic = opaque;  in riscv_imsic_read()  local
258     if (addr > IMSIC_MMIO_SIZE(imsic->num_pages)) {  in riscv_imsic_read()
274     RISCVIMSICState *imsic = opaque;  in riscv_imsic_write()  local
283     if (addr > IMSIC_MMIO_SIZE(imsic->num_pages)) {  in riscv_imsic_write()
291         msi.address_lo = extract64(imsic->mmio.addr + addr, 0, 32);  in riscv_imsic_write()
292         msi.address_hi = extract64(imsic->mmio.addr + addr, 32, 32);  in riscv_imsic_write()
304         if (value && (value < imsic->num_irqs)) {  in riscv_imsic_write()
305             imsic->eistate[(page * imsic->num_irqs) + value] |=  in riscv_imsic_write()
311     riscv_imsic_update(imsic, page);  in riscv_imsic_write()
333     RISCVIMSICState *imsic = RISCV_IMSIC(dev);  in riscv_imsic_realize()  local
334     RISCVCPU *rcpu = RISCV_CPU(cpu_by_arch_id(imsic->hartid));  in riscv_imsic_realize()
335     CPUState *cpu = cpu_by_arch_id(imsic->hartid);  in riscv_imsic_realize()
339         imsic->num_eistate = imsic->num_pages * imsic->num_irqs;  in riscv_imsic_realize()
340         imsic->eidelivery = g_new0(uint32_t, imsic->num_pages);  in riscv_imsic_realize()
341         imsic->eithreshold = g_new0(uint32_t, imsic->num_pages);  in riscv_imsic_realize()
342         imsic->eistate = g_new0(uint32_t, imsic->num_eistate);  in riscv_imsic_realize()
345     memory_region_init_io(&imsic->mmio, OBJECT(dev), &riscv_imsic_ops,  in riscv_imsic_realize()
346                           imsic, TYPE_RISCV_IMSIC,  in riscv_imsic_realize()
347                           IMSIC_MMIO_SIZE(imsic->num_pages));  in riscv_imsic_realize()
348     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &imsic->mmio);  in riscv_imsic_realize()
352             (imsic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) {  in riscv_imsic_realize()
354                    (imsic->mmode) ? "MEIP" : "SEIP");  in riscv_imsic_realize()
359     imsic->external_irqs = g_malloc(sizeof(qemu_irq) * imsic->num_pages);  in riscv_imsic_realize()
360     qdev_init_gpio_out(dev, imsic->external_irqs, imsic->num_pages);  in riscv_imsic_realize()
364         if (!imsic->mmode) {  in riscv_imsic_realize()
366             riscv_cpu_set_geilen(env, imsic->num_pages - 1);  in riscv_imsic_realize()
370         riscv_cpu_set_aia_ireg_rmw_fn(env, (imsic->mmode) ? PRV_M : PRV_S,  in riscv_imsic_realize()
371                                       riscv_imsic_rmw, imsic);  in riscv_imsic_realize()