50     RISCVAclintMTimerState *mtimer = opaque;  in cpu_riscv_read_rtc()  local
51     return cpu_riscv_read_rtc_raw(mtimer->timebase_freq) + mtimer->time_delta;  in cpu_riscv_read_rtc()
58 static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtimer,  in riscv_aclint_mtimer_write_timecmp()  argument
63     uint32_t timebase_freq = mtimer->timebase_freq;  in riscv_aclint_mtimer_write_timecmp()
67     uint64_t rtc = cpu_riscv_read_rtc(mtimer);  in riscv_aclint_mtimer_write_timecmp()
70     hartid = hartid - mtimer->hartid_base;  in riscv_aclint_mtimer_write_timecmp()
72     mtimer->timecmp[hartid] = value;  in riscv_aclint_mtimer_write_timecmp()
73     if (mtimer->timecmp[hartid] <= rtc) {  in riscv_aclint_mtimer_write_timecmp()
78         qemu_irq_raise(mtimer->timer_irqs[hartid]);  in riscv_aclint_mtimer_write_timecmp()
83     qemu_irq_lower(mtimer->timer_irqs[hartid]);  in riscv_aclint_mtimer_write_timecmp()
84     diff = mtimer->timecmp[hartid] - rtc;  in riscv_aclint_mtimer_write_timecmp()
109     timer_mod(mtimer->timers[hartid], next);  in riscv_aclint_mtimer_write_timecmp()
123 /* CPU read MTIMER register */
127     RISCVAclintMTimerState *mtimer = opaque;  in riscv_aclint_mtimer_read()  local
129     if (addr >= mtimer->timecmp_base &&  in riscv_aclint_mtimer_read()
130         addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) {  in riscv_aclint_mtimer_read()
131         size_t hartid = mtimer->hartid_base +  in riscv_aclint_mtimer_read()
132                         ((addr - mtimer->timecmp_base) >> 3);  in riscv_aclint_mtimer_read()
137                           "aclint-mtimer: invalid hartid: %zu", hartid);  in riscv_aclint_mtimer_read()
140             uint64_t timecmp = mtimer->timecmp[hartid];  in riscv_aclint_mtimer_read()
144             uint64_t timecmp = mtimer->timecmp[hartid];  in riscv_aclint_mtimer_read()
148                           "aclint-mtimer: invalid read: %08x", (uint32_t)addr);  in riscv_aclint_mtimer_read()
151     } else if (addr == mtimer->time_base) {  in riscv_aclint_mtimer_read()
153         uint64_t rtc = cpu_riscv_read_rtc(mtimer);  in riscv_aclint_mtimer_read()
155     } else if (addr == mtimer->time_base + 4) {  in riscv_aclint_mtimer_read()
157         return (cpu_riscv_read_rtc(mtimer) >> 32) & 0xFFFFFFFF;  in riscv_aclint_mtimer_read()
161                   "aclint-mtimer: invalid read: %08x", (uint32_t)addr);  in riscv_aclint_mtimer_read()
165 /* CPU write MTIMER register */
169     RISCVAclintMTimerState *mtimer = opaque;  in riscv_aclint_mtimer_write()  local
172     if (addr >= mtimer->timecmp_base &&  in riscv_aclint_mtimer_write()
173         addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) {  in riscv_aclint_mtimer_write()
174         size_t hartid = mtimer->hartid_base +  in riscv_aclint_mtimer_write()
175                         ((addr - mtimer->timecmp_base) >> 3);  in riscv_aclint_mtimer_write()
180                           "aclint-mtimer: invalid hartid: %zu", hartid);  in riscv_aclint_mtimer_write()
184                 uint64_t timecmp_hi = mtimer->timecmp[hartid] >> 32;  in riscv_aclint_mtimer_write()
185                 riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,  in riscv_aclint_mtimer_write()
189                 riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,  in riscv_aclint_mtimer_write()
195                 uint64_t timecmp_lo = mtimer->timecmp[hartid];  in riscv_aclint_mtimer_write()
196                 riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,  in riscv_aclint_mtimer_write()
200                               "aclint-mtimer: invalid timecmp_hi write: %08x",  in riscv_aclint_mtimer_write()
205                           "aclint-mtimer: invalid timecmp write: %08x",  in riscv_aclint_mtimer_write()
209     } else if (addr == mtimer->time_base || addr == mtimer->time_base + 4) {  in riscv_aclint_mtimer_write()
210         uint64_t rtc_r = cpu_riscv_read_rtc_raw(mtimer->timebase_freq);  in riscv_aclint_mtimer_write()
211         uint64_t rtc = cpu_riscv_read_rtc(mtimer);  in riscv_aclint_mtimer_write()
213         if (addr == mtimer->time_base) {  in riscv_aclint_mtimer_write()
216                 mtimer->time_delta = ((rtc & ~0xFFFFFFFFULL) | value) - rtc_r;  in riscv_aclint_mtimer_write()
219                 mtimer->time_delta = value - rtc_r;  in riscv_aclint_mtimer_write()
224                 mtimer->time_delta = (value << 32 | (rtc & 0xFFFFFFFF)) - rtc_r;  in riscv_aclint_mtimer_write()
227                               "aclint-mtimer: invalid time_hi write: %08x",  in riscv_aclint_mtimer_write()
234         for (i = 0; i < mtimer->num_harts; i++) {  in riscv_aclint_mtimer_write()
235             CPUState *cpu = cpu_by_arch_id(mtimer->hartid_base + i);  in riscv_aclint_mtimer_write()
240             riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu),  in riscv_aclint_mtimer_write()
241                                               mtimer->hartid_base + i,  in riscv_aclint_mtimer_write()
242                                               mtimer->timecmp[i]);  in riscv_aclint_mtimer_write()
248                   "aclint-mtimer: invalid write: %08x", (uint32_t)addr);  in riscv_aclint_mtimer_write()
308      *   - On MTIMER device reset, the MTIME register is cleared to zero.  in riscv_aclint_mtimer_reset_enter()
309      *   - On MTIMER device reset, the MTIMECMP registers are in unknown state.  in riscv_aclint_mtimer_reset_enter()
311     RISCVAclintMTimerState *mtimer = RISCV_ACLINT_MTIMER(obj);  in riscv_aclint_mtimer_reset_enter()  local
317     riscv_aclint_mtimer_write(mtimer, mtimer->time_base, 0, 8);  in riscv_aclint_mtimer_reset_enter()
350  * Create ACLINT MTIMER device.