435 static int pnv_xive2_end_update(PnvXive2 *xive, uint8_t watch_engine)  in pnv_xive2_end_update()  argument
442     assert(watch_engine < ARRAY_SIZE(endc_watch));  in pnv_xive2_end_update()
444     spec_reg = (VC_ENDC_WATCH0_SPEC + watch_engine * 0x40) >> 3;  in pnv_xive2_end_update()
445     data_reg = (VC_ENDC_WATCH0_DATA0 + watch_engine * 0x40) >> 3;  in pnv_xive2_end_update()
457 static void pnv_xive2_end_cache_load(PnvXive2 *xive, uint8_t watch_engine)  in pnv_xive2_end_cache_load()  argument
464     assert(watch_engine < ARRAY_SIZE(endc_watch));  in pnv_xive2_end_cache_load()
466     spec_reg = (VC_ENDC_WATCH0_SPEC + watch_engine * 0x40) >> 3;  in pnv_xive2_end_cache_load()
467     data_reg = (VC_ENDC_WATCH0_DATA0 + watch_engine * 0x40) >> 3;  in pnv_xive2_end_cache_load()
513 static int pnv_xive2_nxc_update(PnvXive2 *xive, uint8_t watch_engine)  in pnv_xive2_nxc_update()  argument
520     assert(watch_engine < ARRAY_SIZE(nxc_watch));  in pnv_xive2_nxc_update()
522     spec_reg = (PC_NXC_WATCH0_SPEC + watch_engine * 0x40) >> 3;  in pnv_xive2_nxc_update()
523     data_reg = (PC_NXC_WATCH0_DATA0 + watch_engine * 0x40) >> 3;  in pnv_xive2_nxc_update()
538 static void pnv_xive2_nxc_cache_load(PnvXive2 *xive, uint8_t watch_engine)  in pnv_xive2_nxc_cache_load()  argument
545     assert(watch_engine < ARRAY_SIZE(nxc_watch));  in pnv_xive2_nxc_cache_load()
547     spec_reg = (PC_NXC_WATCH0_SPEC + watch_engine * 0x40) >> 3;  in pnv_xive2_nxc_cache_load()
548     data_reg = (PC_NXC_WATCH0_DATA0 + watch_engine * 0x40) >> 3;  in pnv_xive2_nxc_cache_load()
1145 static void pnv_xive2_cache_watch_release(uint64_t *state, uint8_t watch_engine)  in pnv_xive2_cache_watch_release()  argument
1147     uint8_t engine_bit = 3 - watch_engine;  in pnv_xive2_cache_watch_release()
1176                                                uint8_t watch_engine)  in pnv_xive2_endc_cache_watch_release()  argument
1180     pnv_xive2_cache_watch_release(&state, watch_engine);  in pnv_xive2_endc_cache_watch_release()
1190     uint8_t watch_engine;  in pnv_xive2_ic_vc_read()  local
1236         watch_engine = (offset - VC_ENDC_WATCH0_SPEC) >> 6;  in pnv_xive2_ic_vc_read()
1238         pnv_xive2_endc_cache_watch_release(xive, watch_engine);  in pnv_xive2_ic_vc_read()
1250         watch_engine = (offset - VC_ENDC_WATCH0_DATA0) >> 6;  in pnv_xive2_ic_vc_read()
1251         pnv_xive2_end_cache_load(xive, watch_engine);  in pnv_xive2_ic_vc_read()
1304     uint8_t watch_engine;  in pnv_xive2_ic_vc_write()  local
1368         watch_engine = (offset - VC_ENDC_WATCH0_DATA0) >> 6;  in pnv_xive2_ic_vc_write()
1370         pnv_xive2_end_update(xive, watch_engine);  in pnv_xive2_ic_vc_write()
1446                                               uint8_t watch_engine)  in pnv_xive2_nxc_cache_watch_release()  argument
1450     pnv_xive2_cache_watch_release(&state, watch_engine);  in pnv_xive2_nxc_cache_watch_release()
1460     uint8_t watch_engine;  in pnv_xive2_ic_pc_read()  local
1486         watch_engine = (offset - PC_NXC_WATCH0_SPEC) >> 6;  in pnv_xive2_ic_pc_read()
1488         pnv_xive2_nxc_cache_watch_release(xive, watch_engine);  in pnv_xive2_ic_pc_read()
1500         watch_engine = (offset - PC_NXC_WATCH0_DATA0) >> 6;  in pnv_xive2_ic_pc_read()
1501         pnv_xive2_nxc_cache_load(xive, watch_engine);  in pnv_xive2_ic_pc_read()
1547     uint8_t watch_engine;  in pnv_xive2_ic_pc_write()  local
1589         watch_engine = (offset - PC_NXC_WATCH0_DATA0) >> 6;  in pnv_xive2_ic_pc_write()
1591         pnv_xive2_nxc_update(xive, watch_engine);  in pnv_xive2_ic_pc_write()