Lines Matching +full:intc +full:- +full:nr +full:- +full:irqs
4 * Copyright (c) 2017-2019, IBM Corporation.
7 * COPYING file in the top-level directory.
25 #include "hw/qdev-properties.h"
55 * 0 - IPI,
56 * 1 - HWD,
57 * 2 - First escalate,
58 * 3 - Second escalate,
59 * 4 - Redistribution,
60 * 5 - IPI cascaded queue ?
66 qemu_log_mask(LOG_GUEST_ERROR, "XIVE[%x] - " fmt "\n", \
67 (xive)->chip->chip_id, ## __VA_ARGS__);
76 uint8_t blk = xive->chip->chip_id; in pnv_xive_block_id()
77 uint64_t cfg_val = xive->regs[PC_TCTXT_CFG >> 3]; in pnv_xive_block_id()
110 idx_max = vst_tsize / info->size - 1; in pnv_xive_vst_addr_direct()
114 info->name, idx, idx_max); in pnv_xive_vst_addr_direct()
119 return vst_addr + idx * info->size; in pnv_xive_vst_addr_direct()
136 info->name, idx, vsd_addr); in pnv_xive_vst_addr_indirect()
142 xive_error(xive, "VST: invalid %s entry %x !?", info->name, idx); in pnv_xive_vst_addr_indirect()
150 xive_error(xive, "VST: invalid %s page shift %d", info->name, in pnv_xive_vst_addr_indirect()
155 vst_per_page = (1ull << page_shift) / info->size; in pnv_xive_vst_addr_indirect()
164 PRIx64, info->name, vsd_idx, vsd_addr); in pnv_xive_vst_addr_indirect()
170 xive_error(xive, "VST: invalid %s entry %x !?", info->name, idx); in pnv_xive_vst_addr_indirect()
181 info->name, idx); in pnv_xive_vst_addr_indirect()
208 info->name, blk, idx); in pnv_xive_vst_addr_remote()
212 remote_addr |= ((uint64_t)idx) << xive->pc_shift; in pnv_xive_vst_addr_remote()
231 if (blk >= info->max_blocks) { in pnv_xive_vst_addr()
233 blk, info->name, idx); in pnv_xive_vst_addr()
237 vsd = xive->vsds[type][blk]; in pnv_xive_vst_addr()
259 return -1; in pnv_xive_vst_read()
264 info->size); in pnv_xive_vst_read()
267 " for VST %s %x/%x\n", addr, info->name, blk, idx); in pnv_xive_vst_read()
268 return -1; in pnv_xive_vst_read()
273 #define XIVE_VST_WORD_ALL -1
283 return -1; in pnv_xive_vst_write()
289 info->size); in pnv_xive_vst_write()
299 "for VST %s %x/%x\n", addr, info->name, blk, idx); in pnv_xive_vst_write()
300 return -1; in pnv_xive_vst_write()
312 return -1; in pnv_xive_get_end()
325 return -1; in pnv_xive_write_end()
335 xive->regs[(VC_EQC_CWATCH_SPEC >> 3)]); in pnv_xive_end_update()
337 xive->regs[(VC_EQC_CWATCH_SPEC >> 3)]); in pnv_xive_end_update()
342 eqc_watch[i] = cpu_to_be64(xive->regs[(VC_EQC_CWATCH_DAT0 >> 3) + i]); in pnv_xive_end_update()
352 xive->regs[(VC_EQC_CWATCH_SPEC >> 3)]); in pnv_xive_end_cache_load()
354 xive->regs[(VC_EQC_CWATCH_SPEC >> 3)]); in pnv_xive_end_cache_load()
363 xive->regs[(VC_EQC_CWATCH_DAT0 >> 3) + i] = be64_to_cpu(eqc_watch[i]); in pnv_xive_end_cache_load()
383 xive->regs[(PC_VPC_CWATCH_SPEC >> 3)]); in pnv_xive_nvt_update()
385 xive->regs[(PC_VPC_CWATCH_SPEC >> 3)]); in pnv_xive_nvt_update()
390 vpc_watch[i] = cpu_to_be64(xive->regs[(PC_VPC_CWATCH_DAT0 >> 3) + i]); in pnv_xive_nvt_update()
400 xive->regs[(PC_VPC_CWATCH_SPEC >> 3)]); in pnv_xive_nvt_cache_load()
402 xive->regs[(PC_VPC_CWATCH_SPEC >> 3)]); in pnv_xive_nvt_cache_load()
411 xive->regs[(PC_VPC_CWATCH_DAT0 >> 3) + i] = be64_to_cpu(vpc_watch[i]); in pnv_xive_nvt_cache_load()
425 return -1; in pnv_xive_get_eas()
438 return -1; in pnv_xive_get_pq()
441 *pq = xive_source_esb_get(&xive->ipi_source, idx); in pnv_xive_get_pq()
452 return -1; in pnv_xive_set_pq()
455 *pq = xive_source_esb_set(&xive->ipi_source, idx, *pq); in pnv_xive_set_pq()
461 * the first cores 0-15 (normal) of the chip or 0-7 (fused). The
462 * second register covers cores 16-23 (normal) or 8-11 (fused).
471 return xive->regs[reg >> 3] & PPC_BIT(bit); in pnv_xive_is_cpu_enabled()
480 PnvChip *chip = xive->chip; in pnv_xive_match_nvt()
484 for (i = 0; i < chip->nr_cores; i++) { in pnv_xive_match_nvt()
485 PnvCore *pc = chip->cores[i]; in pnv_xive_match_nvt()
488 for (j = 0; j < cc->nr_threads; j++) { in pnv_xive_match_nvt()
489 PowerPCCPU *cpu = pc->threads[j]; in pnv_xive_match_nvt()
497 tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); in pnv_xive_match_nvt()
508 if (ring != -1) { in pnv_xive_match_nvt()
509 if (match->tctx) { in pnv_xive_match_nvt()
513 return -1; in pnv_xive_match_nvt()
516 match->ring = ring; in pnv_xive_match_nvt()
517 match->tctx = tctx; in pnv_xive_match_nvt()
549 XivePresenter *xptr = XIVE_TCTX(pnv_cpu_state(cpu)->intc)->xptr; in pnv_xive_tm_get_xive()
579 return (~xive->regs[CQ_VC_BARM >> 3] + 1) & CQ_VC_BARM_MASK; in pnv_xive_vc_size()
589 return (~xive->regs[CQ_PC_BARM >> 3] + 1) & CQ_PC_BARM_MASK; in pnv_xive_pc_size()
594 uint64_t vsd = xive->vsds[VST_TSEL_SBE][blk]; in pnv_xive_nr_ipis()
606 uint64_t vsd = xive->vsds[type][blk]; in pnv_xive_vst_per_subpage()
621 info->name, vsd_addr); in pnv_xive_vst_per_subpage()
627 xive_error(xive, "VST: invalid %s entry %x !?", info->name, idx); in pnv_xive_vst_per_subpage()
635 xive_error(xive, "VST: invalid %s page shift %d", info->name, in pnv_xive_vst_per_subpage()
640 return (1ull << page_shift) / info->size; in pnv_xive_vst_per_subpage()
647 * pages and END ESB pages is sub-divided into "sets" which map
664 uint64_t edt_type = GETFIELD(CQ_TDR_EDT_TYPE, xive->edt[i]); in pnv_xive_edt_size()
686 uint64_t edt_type = GETFIELD(CQ_TDR_EDT_TYPE, xive->edt[i]); in pnv_xive_edt_offset()
689 edt_offset -= edt_size; in pnv_xive_edt_offset()
701 memory_region_set_size(&xive->ipi_edt_mmio, ipi_edt_size); in pnv_xive_edt_resize()
702 memory_region_add_subregion(&xive->ipi_mmio, 0, &xive->ipi_edt_mmio); in pnv_xive_edt_resize()
704 memory_region_set_size(&xive->end_edt_mmio, end_edt_size); in pnv_xive_edt_resize()
705 memory_region_add_subregion(&xive->end_mmio, 0, &xive->end_edt_mmio); in pnv_xive_edt_resize()
713 uint64_t tsel = xive->regs[CQ_TAR >> 3] & CQ_TAR_TSEL; in pnv_xive_table_set_data()
714 uint8_t tsel_index = GETFIELD(CQ_TAR_TSEL_INDEX, xive->regs[CQ_TAR >> 3]); in pnv_xive_table_set_data()
720 max_index = ARRAY_SIZE(xive->blk); in pnv_xive_table_set_data()
721 xive_table = xive->blk; in pnv_xive_table_set_data()
724 max_index = ARRAY_SIZE(xive->mig); in pnv_xive_table_set_data()
725 xive_table = xive->mig; in pnv_xive_table_set_data()
728 max_index = ARRAY_SIZE(xive->edt); in pnv_xive_table_set_data()
729 xive_table = xive->edt; in pnv_xive_table_set_data()
732 max_index = ARRAY_SIZE(xive->vdt); in pnv_xive_table_set_data()
733 xive_table = xive->vdt; in pnv_xive_table_set_data()
737 return -1; in pnv_xive_table_set_data()
742 return -1; in pnv_xive_table_set_data()
747 if (xive->regs[CQ_TAR >> 3] & CQ_TAR_TBL_AUTOINC) { in pnv_xive_table_set_data()
748 xive->regs[CQ_TAR >> 3] = in pnv_xive_table_set_data()
749 SETFIELD(CQ_TAR_TSEL_INDEX, xive->regs[CQ_TAR >> 3], ++tsel_index); in pnv_xive_table_set_data()
756 if (tsel == CQ_TAR_TSEL_EDT && tsel_index == ARRAY_SIZE(xive->edt)) { in pnv_xive_table_set_data()
769 XiveENDSource *end_xsrc = &xive->end_source; in pnv_xive_vst_set_exclusive()
770 XiveSource *xsrc = &xive->ipi_source; in pnv_xive_vst_set_exclusive()
779 if (!(xive->regs[VC_GLOBAL_CONFIG >> 3] & VC_GCONF_INDIRECT)) { in pnv_xive_vst_set_exclusive()
781 info->name); in pnv_xive_vst_set_exclusive()
786 xive_error(xive, "VST: invalid %s page shift %d", info->name, in pnv_xive_vst_set_exclusive()
794 " page shift %d", info->name, vst_addr, page_shift); in pnv_xive_vst_set_exclusive()
799 xive->vsds[type][blk] = vsd; in pnv_xive_vst_set_exclusive()
816 memory_region_set_size(&end_xsrc->esb_mmio, (vst_tsize / info->size) in pnv_xive_vst_set_exclusive()
817 * (1ull << xsrc->esb_shift)); in pnv_xive_vst_set_exclusive()
819 memory_region_add_subregion(&xive->end_edt_mmio, 0, in pnv_xive_vst_set_exclusive()
820 &end_xsrc->esb_mmio); in pnv_xive_vst_set_exclusive()
834 memory_region_set_size(&xsrc->esb_mmio, vst_tsize * SBE_PER_BYTE in pnv_xive_vst_set_exclusive()
835 * (1ull << xsrc->esb_shift)); in pnv_xive_vst_set_exclusive()
837 memory_region_add_subregion(&xive->ipi_edt_mmio, 0, &xsrc->esb_mmio); in pnv_xive_vst_set_exclusive()
844 * interrupt fifos of the VC sub-engine in case of overflow. in pnv_xive_vst_set_exclusive()
854 * Both PC and VC sub-engines are configured as each use the Virtual
861 xive->regs[VC_VSD_TABLE_ADDR >> 3]); in pnv_xive_vst_set_data()
863 xive->regs[VC_VSD_TABLE_ADDR >> 3]); in pnv_xive_vst_set_data()
878 * Only take the VC sub-engine configuration into account because in pnv_xive_vst_set_data()
879 * the XiveRouter model combines both VC and PC sub-engines in pnv_xive_vst_set_data()
892 xive->vsds[type][blk] = vsd; in pnv_xive_vst_set_data()
909 * Page 0 sub-engine BARs
910 * 0x000 - 0x3FF IC registers
911 * 0x400 - 0x7FF PC registers
912 * 0x800 - 0xFFF VC registers
915 * 0x000 - 0x7FF HW interrupt triggers (PSI, PHB)
916 * 0x800 - 0xFFF forwards and syncs
921 * Page 4-7 indirect TIMA
925 * IC - registers MMIO
933 bool is_chip0 = xive->chip->chip_id == 0; in pnv_xive_ic_reg_write()
945 xive->pc_shift = 16; in pnv_xive_ic_reg_write()
948 xive->vc_shift = 16; in pnv_xive_ic_reg_write()
953 * TODO: CQ_INT_ADDR_OPT for 1-block-per-chip mode in pnv_xive_ic_reg_write()
994 xive->ipi_source.esb_flags |= XIVE_SRC_STORE_EOI; in pnv_xive_ic_reg_write()
1010 xive->ic_shift = val & CQ_IC_BAR_64K ? 16 : 12; in pnv_xive_ic_reg_write()
1012 xive->ic_base = 0; in pnv_xive_ic_reg_write()
1013 if (xive->regs[reg] & CQ_IC_BAR_VALID) { in pnv_xive_ic_reg_write()
1014 memory_region_del_subregion(&xive->ic_mmio, in pnv_xive_ic_reg_write()
1015 &xive->ic_reg_mmio); in pnv_xive_ic_reg_write()
1016 memory_region_del_subregion(&xive->ic_mmio, in pnv_xive_ic_reg_write()
1017 &xive->ic_notify_mmio); in pnv_xive_ic_reg_write()
1018 memory_region_del_subregion(&xive->ic_mmio, in pnv_xive_ic_reg_write()
1019 &xive->ic_lsi_mmio); in pnv_xive_ic_reg_write()
1020 memory_region_del_subregion(&xive->ic_mmio, in pnv_xive_ic_reg_write()
1021 &xive->tm_indirect_mmio); in pnv_xive_ic_reg_write()
1023 memory_region_del_subregion(sysmem, &xive->ic_mmio); in pnv_xive_ic_reg_write()
1026 xive->ic_base = val & ~(CQ_IC_BAR_VALID | CQ_IC_BAR_64K); in pnv_xive_ic_reg_write()
1027 if (!(xive->regs[reg] & CQ_IC_BAR_VALID)) { in pnv_xive_ic_reg_write()
1028 memory_region_add_subregion(sysmem, xive->ic_base, in pnv_xive_ic_reg_write()
1029 &xive->ic_mmio); in pnv_xive_ic_reg_write()
1031 memory_region_add_subregion(&xive->ic_mmio, 0, in pnv_xive_ic_reg_write()
1032 &xive->ic_reg_mmio); in pnv_xive_ic_reg_write()
1033 memory_region_add_subregion(&xive->ic_mmio, in pnv_xive_ic_reg_write()
1034 1ul << xive->ic_shift, in pnv_xive_ic_reg_write()
1035 &xive->ic_notify_mmio); in pnv_xive_ic_reg_write()
1036 memory_region_add_subregion(&xive->ic_mmio, in pnv_xive_ic_reg_write()
1037 2ul << xive->ic_shift, in pnv_xive_ic_reg_write()
1038 &xive->ic_lsi_mmio); in pnv_xive_ic_reg_write()
1039 memory_region_add_subregion(&xive->ic_mmio, in pnv_xive_ic_reg_write()
1040 4ull << xive->ic_shift, in pnv_xive_ic_reg_write()
1041 &xive->tm_indirect_mmio); in pnv_xive_ic_reg_write()
1048 xive->tm_shift = val & CQ_TM_BAR_64K ? 16 : 12; in pnv_xive_ic_reg_write()
1050 xive->tm_base = 0; in pnv_xive_ic_reg_write()
1051 if (xive->regs[reg] & CQ_TM_BAR_VALID && is_chip0) { in pnv_xive_ic_reg_write()
1052 memory_region_del_subregion(sysmem, &xive->tm_mmio); in pnv_xive_ic_reg_write()
1055 xive->tm_base = val & ~(CQ_TM_BAR_VALID | CQ_TM_BAR_64K); in pnv_xive_ic_reg_write()
1056 if (!(xive->regs[reg] & CQ_TM_BAR_VALID) && is_chip0) { in pnv_xive_ic_reg_write()
1057 memory_region_add_subregion(sysmem, xive->tm_base, in pnv_xive_ic_reg_write()
1058 &xive->tm_mmio); in pnv_xive_ic_reg_write()
1064 xive->regs[reg] = val; in pnv_xive_ic_reg_write()
1065 memory_region_set_size(&xive->pc_mmio, pnv_xive_pc_size(xive)); in pnv_xive_ic_reg_write()
1069 xive->pc_base = 0; in pnv_xive_ic_reg_write()
1070 if (xive->regs[reg] & CQ_PC_BAR_VALID) { in pnv_xive_ic_reg_write()
1071 memory_region_del_subregion(sysmem, &xive->pc_mmio); in pnv_xive_ic_reg_write()
1074 xive->pc_base = val & ~(CQ_PC_BAR_VALID); in pnv_xive_ic_reg_write()
1075 if (!(xive->regs[reg] & CQ_PC_BAR_VALID)) { in pnv_xive_ic_reg_write()
1076 memory_region_add_subregion(sysmem, xive->pc_base, in pnv_xive_ic_reg_write()
1077 &xive->pc_mmio); in pnv_xive_ic_reg_write()
1083 xive->regs[reg] = val; in pnv_xive_ic_reg_write()
1084 memory_region_set_size(&xive->vc_mmio, pnv_xive_vc_size(xive)); in pnv_xive_ic_reg_write()
1088 xive->vc_base = 0; in pnv_xive_ic_reg_write()
1089 if (xive->regs[reg] & CQ_VC_BAR_VALID) { in pnv_xive_ic_reg_write()
1090 memory_region_del_subregion(sysmem, &xive->vc_mmio); in pnv_xive_ic_reg_write()
1093 xive->vc_base = val & ~(CQ_VC_BAR_VALID); in pnv_xive_ic_reg_write()
1094 if (!(xive->regs[reg] & CQ_VC_BAR_VALID)) { in pnv_xive_ic_reg_write()
1095 memory_region_add_subregion(sysmem, xive->vc_base, in pnv_xive_ic_reg_write()
1096 &xive->vc_mmio); in pnv_xive_ic_reg_write()
1140 xive->regs[PC_THREAD_EN_REG0 >> 3] |= val; in pnv_xive_ic_reg_write()
1143 xive->regs[PC_THREAD_EN_REG1 >> 3] |= val; in pnv_xive_ic_reg_write()
1146 xive->regs[PC_THREAD_EN_REG0 >> 3] &= ~val; in pnv_xive_ic_reg_write()
1149 xive->regs[PC_THREAD_EN_REG1 >> 3] &= ~val; in pnv_xive_ic_reg_write()
1173 xive->regs[reg] = val; in pnv_xive_ic_reg_write()
1191 xive->regs[reg] = val; in pnv_xive_ic_reg_write()
1219 xive->regs[reg] = val; in pnv_xive_ic_reg_write()
1271 val = xive->regs[reg]; in pnv_xive_ic_reg_read()
1279 val = xive->regs[PC_THREAD_EN_REG0 >> 3]; in pnv_xive_ic_reg_read()
1283 val = xive->regs[PC_THREAD_EN_REG1 >> 3]; in pnv_xive_ic_reg_read()
1294 xive->regs[reg] = ~(VC_EQC_CWATCH_FULL | VC_EQC_CWATCH_CONFLICT); in pnv_xive_ic_reg_read()
1295 val = xive->regs[reg]; in pnv_xive_ic_reg_read()
1303 val = xive->regs[reg]; in pnv_xive_ic_reg_read()
1306 val = xive->regs[reg]; in pnv_xive_ic_reg_read()
1310 xive->regs[reg] = ~(PC_VPC_CWATCH_FULL | PC_VPC_CWATCH_CONFLICT); in pnv_xive_ic_reg_read()
1311 val = xive->regs[reg]; in pnv_xive_ic_reg_read()
1319 val = xive->regs[reg]; in pnv_xive_ic_reg_read()
1322 val = xive->regs[reg]; in pnv_xive_ic_reg_read()
1328 xive->regs[reg] &= ~VC_SCRUB_VALID; in pnv_xive_ic_reg_read()
1329 val = xive->regs[reg]; in pnv_xive_ic_reg_read()
1336 xive->regs[reg] &= ~PC_AT_KILL_VALID; in pnv_xive_ic_reg_read()
1337 val = xive->regs[reg]; in pnv_xive_ic_reg_read()
1340 xive->regs[reg] &= ~VC_KILL_VALID; in pnv_xive_ic_reg_read()
1341 val = xive->regs[reg]; in pnv_xive_ic_reg_read()
1373 * IC - Notify MMIO port page (write only)
1399 uint8_t end_blk = xive_get_field64(EAS_END_BLOCK, eas->w); in pnv_xive_end_notify()
1400 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); in pnv_xive_end_notify()
1401 uint32_t end_data = xive_get_field64(EAS_END_DATA, eas->w); in pnv_xive_end_notify()
1402 uint64_t end_vsd = xive->vsds[VST_TSEL_EQDT][end_blk]; in pnv_xive_end_notify()
1414 be64_to_cpu(eas->w); in pnv_xive_end_notify()
1476 /* VC: Forwarded IRQs */ in pnv_xive_ic_notify_write()
1482 /* TODO: forwarded IRQs. Should be like HW triggers */ in pnv_xive_ic_notify_write()
1513 return -1; in pnv_xive_ic_notify_read()
1531 * IC - LSI MMIO handlers (not modeled)
1547 return -1; in pnv_xive_ic_lsi_read()
1565 * IC - Indirect TIMA MMIO handlers
1575 PnvChip *chip = xive->chip; in pnv_xive_get_indirect_tctx()
1576 uint64_t tctxt_indir = xive->regs[PC_TCTXT_INDIR0 >> 3]; in pnv_xive_get_indirect_tctx()
1585 pir = (chip->chip_id << 8) | GETFIELD(PC_TCTXT_INDIR_THRDID, tctxt_indir); in pnv_xive_get_indirect_tctx()
1597 return XIVE_TCTX(pnv_cpu_state(cpu)->intc); in pnv_xive_get_indirect_tctx()
1635 XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); in pnv_xive_tm_write()
1644 XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); in pnv_xive_tm_read()
1709 uint64_t ret = -1; in pnv_xive_vc_read()
1712 edt_type = GETFIELD(CQ_TDR_EDT_TYPE, xive->edt[edt_index]); in pnv_xive_vc_read()
1717 edt_as = &xive->ipi_as; in pnv_xive_vc_read()
1720 edt_as = &xive->end_as; in pnv_xive_vc_read()
1724 return -1; in pnv_xive_vc_read()
1734 xive_error(xive, "VC: %s read failed at @0x%"HWADDR_PRIx " -> @0x%" in pnv_xive_vc_read()
1737 return -1; in pnv_xive_vc_read()
1754 edt_type = GETFIELD(CQ_TDR_EDT_TYPE, xive->edt[edt_index]); in pnv_xive_vc_write()
1759 edt_as = &xive->ipi_as; in pnv_xive_vc_write()
1762 edt_as = &xive->end_as; in pnv_xive_vc_write()
1804 uint32_t nvt_idx = offset >> xive->pc_shift; in pnv_xive_pc_read()
1805 uint8_t blk = pnv_xive_block_id(xive); /* TODO: VDT -> block xlate */ in pnv_xive_pc_read()
1835 uint8_t eq_blk = xive_get_field32(NVT_W1_EQ_BLOCK, nvt->w1); in xive_nvt_pic_print_info()
1836 uint32_t eq_idx = xive_get_field32(NVT_W1_EQ_INDEX, nvt->w1); in xive_nvt_pic_print_info()
1844 xive_get_field32(NVT_W4_IPB, nvt->w4)); in xive_nvt_pic_print_info()
1851 uint8_t chip_id = xive->chip->chip_id; in pnv_xive_pic_print_info()
1861 chip_id, blk, srcno0, srcno0 + nr_ipis - 1); in pnv_xive_pic_print_info()
1862 xive_source_pic_print_info(&xive->ipi_source, srcno0, buf); in pnv_xive_pic_print_info()
1865 chip_id, blk, srcno0, srcno0 + nr_ipis - 1); in pnv_xive_pic_print_info()
1889 chip_id, blk, 0, XIVE_NVT_COUNT - 1); in pnv_xive_pic_print_info()
1901 XiveSource *xsrc = &xive->ipi_source; in pnv_xive_reset()
1902 XiveENDSource *end_xsrc = &xive->end_source; in pnv_xive_reset()
1905 xive->ic_shift = xive->vc_shift = xive->pc_shift = 12; in pnv_xive_reset()
1908 if (memory_region_is_mapped(&xsrc->esb_mmio)) { in pnv_xive_reset()
1909 memory_region_del_subregion(&xive->ipi_edt_mmio, &xsrc->esb_mmio); in pnv_xive_reset()
1912 if (memory_region_is_mapped(&xive->ipi_edt_mmio)) { in pnv_xive_reset()
1913 memory_region_del_subregion(&xive->ipi_mmio, &xive->ipi_edt_mmio); in pnv_xive_reset()
1916 if (memory_region_is_mapped(&end_xsrc->esb_mmio)) { in pnv_xive_reset()
1917 memory_region_del_subregion(&xive->end_edt_mmio, &end_xsrc->esb_mmio); in pnv_xive_reset()
1920 if (memory_region_is_mapped(&xive->end_edt_mmio)) { in pnv_xive_reset()
1921 memory_region_del_subregion(&xive->end_mmio, &xive->end_edt_mmio); in pnv_xive_reset()
1929 object_initialize_child(obj, "ipi_source", &xive->ipi_source, in pnv_xive_init()
1931 object_initialize_child(obj, "end_source", &xive->end_source, in pnv_xive_init()
1936 * Maximum number of IRQs and ENDs supported by HW
1945 XiveSource *xsrc = &xive->ipi_source; in pnv_xive_realize()
1946 XiveENDSource *end_xsrc = &xive->end_source; in pnv_xive_realize()
1949 pxc->parent_realize(dev, &local_err); in pnv_xive_realize()
1955 assert(xive->chip); in pnv_xive_realize()
1963 object_property_set_int(OBJECT(xsrc), "nr-irqs", PNV_XIVE_NR_IRQS, in pnv_xive_realize()
1970 object_property_set_int(OBJECT(end_xsrc), "nr-ends", PNV_XIVE_NR_ENDS, in pnv_xive_realize()
1979 xive->ic_shift = xive->vc_shift = xive->pc_shift = 12; in pnv_xive_realize()
1982 memory_region_init_io(&xive->xscom_regs, OBJECT(dev), &pnv_xive_xscom_ops, in pnv_xive_realize()
1983 xive, "xscom-xive", PNV9_XSCOM_XIVE_SIZE << 3); in pnv_xive_realize()
1986 memory_region_init(&xive->ic_mmio, OBJECT(dev), "xive-ic", in pnv_xive_realize()
1989 memory_region_init_io(&xive->ic_reg_mmio, OBJECT(dev), &pnv_xive_ic_reg_ops, in pnv_xive_realize()
1990 xive, "xive-ic-reg", 1 << xive->ic_shift); in pnv_xive_realize()
1991 memory_region_init_io(&xive->ic_notify_mmio, OBJECT(dev), in pnv_xive_realize()
1993 xive, "xive-ic-notify", 1 << xive->ic_shift); in pnv_xive_realize()
1994 xive->ic_notify_mmio.disable_reentrancy_guard = true; in pnv_xive_realize()
1997 memory_region_init_io(&xive->ic_lsi_mmio, OBJECT(dev), &pnv_xive_ic_lsi_ops, in pnv_xive_realize()
1998 xive, "xive-ic-lsi", 2 << xive->ic_shift); in pnv_xive_realize()
2001 memory_region_init_io(&xive->tm_indirect_mmio, OBJECT(dev), in pnv_xive_realize()
2003 xive, "xive-tima-indirect", PNV9_XIVE_TM_SIZE); in pnv_xive_realize()
2010 memory_region_init_io(&xive->vc_mmio, OBJECT(xive), &pnv_xive_vc_ops, xive, in pnv_xive_realize()
2011 "xive-vc", PNV9_XIVE_VC_SIZE); in pnv_xive_realize()
2013 memory_region_init(&xive->ipi_mmio, OBJECT(xive), "xive-vc-ipi", in pnv_xive_realize()
2015 address_space_init(&xive->ipi_as, &xive->ipi_mmio, "xive-vc-ipi"); in pnv_xive_realize()
2016 memory_region_init(&xive->end_mmio, OBJECT(xive), "xive-vc-end", in pnv_xive_realize()
2018 address_space_init(&xive->end_as, &xive->end_mmio, "xive-vc-end"); in pnv_xive_realize()
2024 memory_region_init(&xive->ipi_edt_mmio, OBJECT(xive), "xive-vc-ipi-edt", 0); in pnv_xive_realize()
2025 memory_region_init(&xive->end_edt_mmio, OBJECT(xive), "xive-vc-end-edt", 0); in pnv_xive_realize()
2028 memory_region_init_io(&xive->pc_mmio, OBJECT(xive), &pnv_xive_pc_ops, xive, in pnv_xive_realize()
2029 "xive-pc", PNV9_XIVE_PC_SIZE); in pnv_xive_realize()
2030 xive->pc_mmio.disable_reentrancy_guard = true; in pnv_xive_realize()
2033 memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &pnv_xive_tm_ops, in pnv_xive_realize()
2034 xive, "xive-tima", PNV9_XIVE_TM_SIZE); in pnv_xive_realize()
2042 const char compat[] = "ibm,power9-xive-x"; in pnv_xive_dt_xscom()
2063 DEFINE_PROP_UINT64("ic-bar", PnvXive, ic_base, 0),
2064 DEFINE_PROP_UINT64("vc-bar", PnvXive, vc_base, 0),
2065 DEFINE_PROP_UINT64("pc-bar", PnvXive, pc_base, 0),
2066 DEFINE_PROP_UINT64("tm-bar", PnvXive, tm_base, 0),
2081 xdc->dt_xscom = pnv_xive_dt_xscom; in pnv_xive_class_init()
2083 dc->desc = "PowerNV XIVE Interrupt Controller"; in pnv_xive_class_init()
2084 device_class_set_parent_realize(dc, pnv_xive_realize, &pxc->parent_realize); in pnv_xive_class_init()
2085 dc->realize = pnv_xive_realize; in pnv_xive_class_init()
2088 xrc->get_eas = pnv_xive_get_eas; in pnv_xive_class_init()
2089 xrc->get_pq = pnv_xive_get_pq; in pnv_xive_class_init()
2090 xrc->set_pq = pnv_xive_set_pq; in pnv_xive_class_init()
2091 xrc->get_end = pnv_xive_get_end; in pnv_xive_class_init()
2092 xrc->write_end = pnv_xive_write_end; in pnv_xive_class_init()
2093 xrc->get_nvt = pnv_xive_get_nvt; in pnv_xive_class_init()
2094 xrc->write_nvt = pnv_xive_write_nvt; in pnv_xive_class_init()
2095 xrc->get_block_id = pnv_xive_get_block_id; in pnv_xive_class_init()
2096 xrc->end_notify = pnv_xive_end_notify; in pnv_xive_class_init()
2098 xnc->notify = pnv_xive_notify; in pnv_xive_class_init()
2099 xpc->match_nvt = pnv_xive_match_nvt; in pnv_xive_class_init()
2100 xpc->get_config = pnv_xive_presenter_get_config; in pnv_xive_class_init()