42         VMSTATE_UINT64(pending, IMXAVICState),
63     uint64_t new = s->pending & s->enabled;  in imx_avic_update()
76      * Take interrupt if there's a pending interrupt with  in imx_avic_update()
97         s->pending |= (1ULL << irq);  in imx_avic_set_irq()
101         s->pending &= ~(1ULL << irq);  in imx_avic_set_irq()
153          * one pending IRQ with the same priority,  in imx_avic_read()
156         uint64_t flags = s->pending & s->enabled & ~s->is_fiq;  in imx_avic_read()
177         uint64_t flags = s->pending & s->enabled & s->is_fiq;  in imx_avic_read()
186         return s->pending >> 32;  in imx_avic_read()
189         return s->pending & 0xffffffffULL;  in imx_avic_read()
195     case 22:/* Normal Interrupt Pending Register High */  in imx_avic_read()
196         return (s->pending & s->enabled & ~s->is_fiq) >> 32;  in imx_avic_read()
198     case 23:/* Normal Interrupt Pending Register Low */  in imx_avic_read()
199         return (s->pending & s->enabled & ~s->is_fiq) & 0xffffffffULL;  in imx_avic_read()
201     case 24: /* Fast Interrupt Pending Register High  */  in imx_avic_read()
202         return (s->pending & s->enabled & s->is_fiq) >> 32;  in imx_avic_read()
204     case 25: /* Fast Interrupt Pending Register Low  */  in imx_avic_read()
205         return (s->pending & s->enabled & s->is_fiq) & 0xffffffffULL;  in imx_avic_read()
290         s->pending = (s->pending & 0xffffffffULL) | (val << 32);  in imx_avic_write()
294         s->pending = (s->pending & 0xffffffff00000000ULL) | val;  in imx_avic_write()
297     case 22:/* Normal Interrupt Pending Register High */  in imx_avic_write()
298     case 23:/* Normal Interrupt Pending Register Low */  in imx_avic_write()
299     case 24: /* Fast Interrupt Pending Register High  */  in imx_avic_write()
300     case 25: /* Fast Interrupt Pending Register Low  */  in imx_avic_write()
320     s->pending = 0;  in imx_avic_reset()