hw/intc/gic_internal.h

2  * ARM GIC support - internal interfaces
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 #define ALL_CPU_MASK ((unsigned)(((1 << GIC_NCPU) - 1)))
29 #define GIC_DIST_SET_ENABLED(irq, cm) (s->irq_state[irq].enabled |= (cm))
30 #define GIC_DIST_CLEAR_ENABLED(irq, cm) (s->irq_state[irq].enabled &= ~(cm))
31 #define GIC_DIST_TEST_ENABLED(irq, cm) ((s->irq_state[irq].enabled & (cm)) != 0)
32 #define GIC_DIST_SET_PENDING(irq, cm) (s->irq_state[irq].pending |= (cm))
33 #define GIC_DIST_CLEAR_PENDING(irq, cm) (s->irq_state[irq].pending &= ~(cm))
34 #define GIC_DIST_SET_ACTIVE(irq, cm) (s->irq_state[irq].active |= (cm))
35 #define GIC_DIST_CLEAR_ACTIVE(irq, cm) (s->irq_state[irq].active &= ~(cm))
36 #define GIC_DIST_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0)
37 #define GIC_DIST_SET_MODEL(irq) (s->irq_state[irq].model = true)
38 #define GIC_DIST_CLEAR_MODEL(irq) (s->irq_state[irq].model = false)
39 #define GIC_DIST_TEST_MODEL(irq) (s->irq_state[irq].model)
40 #define GIC_DIST_SET_LEVEL(irq, cm) (s->irq_state[irq].level |= (cm))
41 #define GIC_DIST_CLEAR_LEVEL(irq, cm) (s->irq_state[irq].level &= ~(cm))
42 #define GIC_DIST_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0)
43 #define GIC_DIST_SET_EDGE_TRIGGER(irq) (s->irq_state[irq].edge_trigger = true)
45     (s->irq_state[irq].edge_trigger = false)
46 #define GIC_DIST_TEST_EDGE_TRIGGER(irq) (s->irq_state[irq].edge_trigger)
48                                     s->priority1[irq][cpu] :            \
49                                     s->priority2[(irq) - GIC_INTERNAL])
50 #define GIC_DIST_TARGET(irq) (s->irq_target[irq])
51 #define GIC_DIST_CLEAR_GROUP(irq, cm) (s->irq_state[irq].group &= ~(cm))
52 #define GIC_DIST_SET_GROUP(irq, cm) (s->irq_state[irq].group |= (cm))
53 #define GIC_DIST_TEST_GROUP(irq, cm) ((s->irq_state[irq].group & (cm)) != 0)
67     FIELD(GICH_HCR, EN, 0, 1)
68     FIELD(GICH_HCR, UIE, 1, 1)
69     FIELD(GICH_HCR, LRENPIE, 2, 1)
70     FIELD(GICH_HCR, NPIE, 3, 1)
71     FIELD(GICH_HCR, VGRP0EIE, 4, 1)
72     FIELD(GICH_HCR, VGRP0DIE, 5, 1)
73     FIELD(GICH_HCR, VGRP1EIE, 6, 1)
74     FIELD(GICH_HCR, VGRP1DIE, 7, 1)
75     FIELD(GICH_HCR, EOICount, 27, 5)
85     FIELD(GICH_VTR, ListRegs, 0, 6)
86     FIELD(GICH_VTR, PREbits, 26, 3)
87     FIELD(GICH_VTR, PRIbits, 29, 3)
90     FIELD(GICH_VMCR, VMCCtlr, 0, 10)
91     FIELD(GICH_VMCR, VMABP, 18, 3)
92     FIELD(GICH_VMCR, VMBP, 21, 3)
93     FIELD(GICH_VMCR, VMPriMask, 27, 5)
96     FIELD(GICH_MISR, EOI, 0, 1)
97     FIELD(GICH_MISR, U, 1, 1)
98     FIELD(GICH_MISR, LRENP, 2, 1)
99     FIELD(GICH_MISR, NP, 3, 1)
100     FIELD(GICH_MISR, VGrp0E, 4, 1)
101     FIELD(GICH_MISR, VGrp0D, 5, 1)
102     FIELD(GICH_MISR, VGrp1E, 6, 1)
103     FIELD(GICH_MISR, VGrp1D, 7, 1)
112     FIELD(GICH_LR0, VirtualID, 0, 10)
113     FIELD(GICH_LR0, PhysicalID, 10, 10)
114     FIELD(GICH_LR0, CPUID, 10, 3)
115     FIELD(GICH_LR0, EOI, 19, 1)
116     FIELD(GICH_LR0, Priority, 23, 5)
117     FIELD(GICH_LR0, State, 28, 2)
118     FIELD(GICH_LR0, Grp1, 30, 1)
119     FIELD(GICH_LR0, HW, 31, 1)
168     if (s->revision == REV_11MPCORE) {  in gic_test_pending()
169         return s->irq_state[irq].pending & cm;  in gic_test_pending()
171         /* Edge-triggered interrupts are marked pending on a rising edge, but  in gic_test_pending()
172          * level-triggered interrupts are either considered pending when the  in gic_test_pending()
173          * level is active or if software has explicitly written to  in gic_test_pending()
176         return (s->irq_state[irq].pending & cm) ||  in gic_test_pending()
188     return (cpu >= GIC_NCPU) ? (cpu - GIC_NCPU) : cpu;  in gic_get_vcpu_real_id()
191 /* Return true if the given vIRQ state exists in a LR and is either active or
192  * pending and active.
196  * already acknowledged vIRQ (i.e. has the active bit set in its state).
203     for (lr_idx = 0; lr_idx < s->num_lrs; lr_idx++) {  in gic_virq_is_valid()
204         uint32_t *entry = &s->h_lr[lr_idx][cpu];  in gic_virq_is_valid()
220  *   - Either the corresponding vIRQ has been validated with gic_virq_is_valid()
221  *     so it is `active' or `active and pending',
222  *   - Or it was pending and has been selected by gic_get_best_virq(). It is now
223  *     `pending', `active' or `active and pending', depending on what the guest
234     for (lr_idx = 0; lr_idx < s->num_lrs; lr_idx++) {  in gic_get_lr_entry()
235         uint32_t *entry = &s->h_lr[lr_idx][cpu];  in gic_get_lr_entry()
263          * interrupts. (level triggered interrupts with an active line  in gic_clear_pending()
305             if (!s->security_extn || GIC_DIST_TEST_GROUP(phys_irq, 1 << rcpu)) {  in gic_clear_active()