69         VMSTATE_STRUCT_ARRAY(group, Exynos4210CombinerState, IIC_NGRP, 0,
104         val |= s->group[grp_quad_base_n].src_pending;  in exynos4210_combiner_read()
105         val |= s->group[grp_quad_base_n + 1].src_pending << 8;  in exynos4210_combiner_read()
106         val |= s->group[grp_quad_base_n + 2].src_pending << 16;  in exynos4210_combiner_read()
107         val |= s->group[grp_quad_base_n + 3].src_pending << 24;  in exynos4210_combiner_read()
111         val |= s->group[grp_quad_base_n].src_mask &  in exynos4210_combiner_read()
112         s->group[grp_quad_base_n].src_pending;  in exynos4210_combiner_read()
113         val |= (s->group[grp_quad_base_n + 1].src_mask &  in exynos4210_combiner_read()
114                 s->group[grp_quad_base_n + 1].src_pending) << 8;  in exynos4210_combiner_read()
115         val |= (s->group[grp_quad_base_n + 2].src_mask &  in exynos4210_combiner_read()
116                 s->group[grp_quad_base_n + 2].src_pending) << 16;  in exynos4210_combiner_read()
117         val |= (s->group[grp_quad_base_n + 3].src_mask &  in exynos4210_combiner_read()
118                 s->group[grp_quad_base_n + 3].src_pending) << 24;  in exynos4210_combiner_read()
136     if (s->group[group_n].src_mask & s->group[group_n].src_pending) {  in exynos4210_combiner_update()
217         s->group[grp_quad_base_n].src_mask |= val & 0xFF;  in exynos4210_combiner_write()
218         s->group[grp_quad_base_n + 1].src_mask |= (val & 0xFF00) >> 8;  in exynos4210_combiner_write()
219         s->group[grp_quad_base_n + 2].src_mask |= (val & 0xFF0000) >> 16;  in exynos4210_combiner_write()
220         s->group[grp_quad_base_n + 3].src_mask |= (val & 0xFF000000) >> 24;  in exynos4210_combiner_write()
237         s->group[grp_quad_base_n].src_mask &= ~(val & 0xFF);  in exynos4210_combiner_write()
238         s->group[grp_quad_base_n + 1].src_mask &= ~((val & 0xFF00) >> 8);  in exynos4210_combiner_write()
239         s->group[grp_quad_base_n + 2].src_mask &= ~((val & 0xFF0000) >> 16);  in exynos4210_combiner_write()
240         s->group[grp_quad_base_n + 3].src_mask &= ~((val & 0xFF000000) >> 24);  in exynos4210_combiner_write()
277         s->group[group_n].src_pending |= 1 << bit_n;  in exynos4210_combiner_handler()
279         s->group[group_n].src_pending &= ~(1 << bit_n);  in exynos4210_combiner_handler()
289     memset(&s->group, 0, sizeof(s->group));  in exynos4210_combiner_reset()