9  * the COPYING file in the top-level directory.
24  * Additionally, the "Interrupt Enable", "Edge Status" and "Software Interrupt"
27  * read-modify-write sequence).
47     uint64_t new = (s->raw & s->enable);  in aspeed_vic_update()
50     flags = new & s->select;  in aspeed_vic_update()
52     qemu_set_irq(s->fiq, !!flags);  in aspeed_vic_update()
54     flags = new & ~s->select;  in aspeed_vic_update()
56     qemu_set_irq(s->irq, !!flags);  in aspeed_vic_update()
74     if (s->sense & irq_mask) {  in aspeed_vic_set_irq()
75         /* level-triggered */  in aspeed_vic_set_irq()
76         if (s->event & irq_mask) {  in aspeed_vic_set_irq()
77             /* high-sensitive */  in aspeed_vic_set_irq()
80             /* low-sensitive */  in aspeed_vic_set_irq()
83         s->raw = deposit64(s->raw, irq, 1, raise);  in aspeed_vic_set_irq()
85         uint64_t old_level = s->level & irq_mask;  in aspeed_vic_set_irq()
87         /* edge-triggered */  in aspeed_vic_set_irq()
88         if (s->dual_edge & irq_mask) {  in aspeed_vic_set_irq()
91             if (s->event & irq_mask) {  in aspeed_vic_set_irq()
92                 /* rising-sensitive */  in aspeed_vic_set_irq()
95                 /* falling-sensitive */  in aspeed_vic_set_irq()
100             s->raw = deposit64(s->raw, irq, 1, raise);  in aspeed_vic_set_irq()
103     s->level = deposit64(s->level, irq, 1, level);  in aspeed_vic_set_irq()
125         val = s->raw & ~s->select & s->enable;  in aspeed_vic_read()
129         val = s->raw & s->select & s->enable;  in aspeed_vic_read()
133         val = s->raw;  in aspeed_vic_read()
137         val = s->select;  in aspeed_vic_read()
141         val = s->enable;  in aspeed_vic_read()
145         val = s->trigger;  in aspeed_vic_read()
149         val = s->sense;  in aspeed_vic_read()
151     case 0xc8: /* Interrupt Both Edge Trigger Control */  in aspeed_vic_read()
153         val = s->dual_edge;  in aspeed_vic_read()
157         val = s->event;  in aspeed_vic_read()
159     case 0xe0: /* Edge Triggered Interrupt Status */  in aspeed_vic_read()
160         val = s->raw & ~s->sense;  in aspeed_vic_read()
165     case 0xd8: /* Edge Triggered Interrupt Clear */  in aspeed_vic_read()
167                       "%s: Read of write-only register with offset 0x%"  in aspeed_vic_read()
218         /* Register has deposit64() semantics - overwrite requested 32 bits */  in aspeed_vic_write()
220             s->select &= AVIC_L_MASK;  in aspeed_vic_write()
222             s->select &= ((uint64_t) AVIC_H_MASK) << 32;  in aspeed_vic_write()
224         s->select |= data;  in aspeed_vic_write()
228         s->enable |= data;  in aspeed_vic_write()
232         s->enable &= ~data;  in aspeed_vic_write()
245         /* Register has deposit64() semantics - overwrite the top four valid  in aspeed_vic_write()
249             s->event &= ~AVIC_EVENT_W_MASK;  in aspeed_vic_write()
250             s->event |= (data & AVIC_EVENT_W_MASK);  in aspeed_vic_write()
256     case 0xd8: /* Edge Triggered Interrupt Clear */  in aspeed_vic_write()
258         s->raw &= ~(data & ~s->sense);  in aspeed_vic_write()
268     case 0xc8: /* Interrupt Both Edge Trigger Control */  in aspeed_vic_write()
270     case 0xe0: /* Edge Triggered Interrupt Status */  in aspeed_vic_write()
272                       "%s: Write of read-only register with offset 0x%"  in aspeed_vic_write()
298     s->level = 0;  in aspeed_vic_reset()
299     s->raw = 0;  in aspeed_vic_reset()
300     s->select = 0;  in aspeed_vic_reset()
301     s->enable = 0;  in aspeed_vic_reset()
302     s->trigger = 0;  in aspeed_vic_reset()
303     s->sense = 0x1F07FFF8FFFFULL;  in aspeed_vic_reset()
304     s->dual_edge = 0xF800070000ULL;  in aspeed_vic_reset()
305     s->event = 0x5F07FFF8FFFFULL;  in aspeed_vic_reset()
315     memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_vic_ops, s,  in aspeed_vic_realize()
318     sysbus_init_mmio(sbd, &s->iomem);  in aspeed_vic_realize()
321     sysbus_init_irq(sbd, &s->irq);  in aspeed_vic_realize()
322     sysbus_init_irq(sbd, &s->fiq);  in aspeed_vic_realize()
326     .name = "aspeed.new-vic",
345     dc->realize = aspeed_vic_realize;  in aspeed_vic_class_init()
347     dc->desc = "ASPEED Interrupt Controller (New)";  in aspeed_vic_class_init()
348     dc->vmsd = &vmstate_aspeed_vic;  in aspeed_vic_class_init()