Lines Matching refs:value
1516 uint32_t value = cpu->env.v7m.fpccr[M_REG_S]; in nvic_readl() local
1525 value &= mask; in nvic_readl()
1527 value |= cpu->env.v7m.fpccr[M_REG_NS]; in nvic_readl()
1528 return value; in nvic_readl()
1553 static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, in nvic_writel() argument
1577 s->itns[startvec + i] = (value >> i) & 1; in nvic_writel()
1584 if (value & (1 << 31)) { in nvic_writel()
1586 } else if (value & (1 << 30) && in nvic_writel()
1592 if (value & (1 << 28)) { in nvic_writel()
1594 } else if (value & (1 << 27)) { in nvic_writel()
1597 if (value & (1 << 26)) { in nvic_writel()
1599 } else if (value & (1 << 25)) { in nvic_writel()
1604 cpu->env.v7m.vecbase[attrs.secure] = value & 0xffffff80; in nvic_writel()
1607 if ((value >> R_V7M_AIRCR_VECTKEY_SHIFT) == 0x05fa) { in nvic_writel()
1608 if (value & R_V7M_AIRCR_SYSRESETREQ_MASK) { in nvic_writel()
1614 if (value & R_V7M_AIRCR_VECTCLRACTIVE_MASK) { in nvic_writel()
1619 if (value & R_V7M_AIRCR_VECTRESET_MASK) { in nvic_writel()
1627 extract32(value, in nvic_writel()
1634 cpu->env.v7m.aircr = value & in nvic_writel()
1662 value &= ~(R_V7M_SCR_SLEEPDEEP_MASK | R_V7M_SCR_SLEEPDEEPS_MASK); in nvic_writel()
1663 cpu->env.v7m.scr[attrs.secure] = value; in nvic_writel()
1684 value &= mask; in nvic_writel()
1688 value |= R_V7M_CCR_NONBASETHRDENA_MASK in nvic_writel()
1695 | (value & R_V7M_CCR_BFHFNMIGN_MASK); in nvic_writel()
1696 value &= ~R_V7M_CCR_BFHFNMIGN_MASK; in nvic_writel()
1703 value &= ~R_V7M_CCR_BFHFNMIGN_MASK; in nvic_writel()
1704 value |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK; in nvic_writel()
1708 cpu->env.v7m.ccr[attrs.secure] = value; in nvic_writel()
1716 s->sec_vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0; in nvic_writel()
1718 s->sec_vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0; in nvic_writel()
1719 s->sec_vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0; in nvic_writel()
1721 (value & (1 << 10)) != 0; in nvic_writel()
1723 (value & (1 << 11)) != 0; in nvic_writel()
1725 (value & (1 << 12)) != 0; in nvic_writel()
1726 s->sec_vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0; in nvic_writel()
1727 s->sec_vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0; in nvic_writel()
1728 s->sec_vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0; in nvic_writel()
1729 s->sec_vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0; in nvic_writel()
1731 (value & (1 << 18)) != 0; in nvic_writel()
1732 s->sec_vectors[ARMV7M_EXCP_HARD].pending = (value & (1 << 21)) != 0; in nvic_writel()
1734 s->vectors[ARMV7M_EXCP_SECURE].active = (value & (1 << 4)) != 0; in nvic_writel()
1735 s->vectors[ARMV7M_EXCP_SECURE].enabled = (value & (1 << 19)) != 0; in nvic_writel()
1736 s->vectors[ARMV7M_EXCP_SECURE].pending = (value & (1 << 20)) != 0; in nvic_writel()
1738 s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0; in nvic_writel()
1741 s->vectors[ARMV7M_EXCP_HARD].pending = (value & (1 << 21)) != 0; in nvic_writel()
1743 s->vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0; in nvic_writel()
1744 s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0; in nvic_writel()
1745 s->vectors[ARMV7M_EXCP_PENDSV].active = (value & (1 << 10)) != 0; in nvic_writel()
1746 s->vectors[ARMV7M_EXCP_SYSTICK].active = (value & (1 << 11)) != 0; in nvic_writel()
1747 s->vectors[ARMV7M_EXCP_USAGE].pending = (value & (1 << 12)) != 0; in nvic_writel()
1748 s->vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0; in nvic_writel()
1749 s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0; in nvic_writel()
1750 s->vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0; in nvic_writel()
1751 s->vectors[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0; in nvic_writel()
1754 s->vectors[ARMV7M_EXCP_BUS].active = (value & (1 << 1)) != 0; in nvic_writel()
1755 s->vectors[ARMV7M_EXCP_BUS].pending = (value & (1 << 14)) != 0; in nvic_writel()
1756 s->vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0; in nvic_writel()
1763 (value & (1 << 5)) == 0) { in nvic_writel()
1774 (value & (1 << 2)) == 0) { in nvic_writel()
1779 s->vectors[ARMV7M_EXCP_DEBUG].active = (value & (1 << 8)) != 0; in nvic_writel()
1786 cpu->env.v7m.hfsr &= ~value; /* W1C */ in nvic_writel()
1789 cpu->env.v7m.dfsr &= ~value; /* W1C */ in nvic_writel()
1795 cpu->env.v7m.mmfar[attrs.secure] = value; in nvic_writel()
1805 cpu->env.v7m.bfar = value; in nvic_writel()
1813 cpu->env.v7m.csselr[attrs.secure] = value & R_V7M_CSSELR_INDEX_MASK; in nvic_writel()
1819 cpu->env.v7m.cpacr[attrs.secure] = value & (0xf << 20); in nvic_writel()
1825 cpu->env.v7m.nsacr = value & (3 << 10); in nvic_writel()
1831 if ((value & in nvic_writel()
1838 = value & (R_V7M_MPU_CTRL_ENABLE_MASK | in nvic_writel()
1844 if (value >= cpu->pmsav7_dregion) { in nvic_writel()
1847 value, cpu->pmsav7_dregion); in nvic_writel()
1849 cpu->env.pmsav7.rnr[attrs.secure] = value; in nvic_writel()
1874 cpu->env.pmsav8.rbar[attrs.secure][region] = value; in nvic_writel()
1879 if (value & (1 << 4)) { in nvic_writel()
1883 region = extract32(value, 0, 4); in nvic_writel()
1899 cpu->env.pmsav7.drbar[region] = value & ~0x1f; in nvic_writel()
1924 cpu->env.pmsav8.rlar[attrs.secure][region] = value; in nvic_writel()
1933 cpu->env.pmsav7.drsr[region] = value & 0xff3f; in nvic_writel()
1934 cpu->env.pmsav7.dracr[region] = (value >> 16) & 0x173f; in nvic_writel()
1944 cpu->env.pmsav8.mair0[attrs.secure] = value; in nvic_writel()
1956 cpu->env.pmsav8.mair1[attrs.secure] = value; in nvic_writel()
1969 cpu->env.sau.ctrl = value & 3; in nvic_writel()
1983 if (value >= cpu->sau_sregion) { in nvic_writel()
1986 value, cpu->sau_sregion); in nvic_writel()
1988 cpu->env.sau.rnr = value; in nvic_writel()
2004 cpu->env.sau.rbar[region] = value & ~0x1f; in nvic_writel()
2021 cpu->env.sau.rlar[region] = value & ~0x1c; in nvic_writel()
2032 cpu->env.v7m.sfsr &= ~value; /* W1C */ in nvic_writel()
2041 cpu->env.v7m.sfsr = value; in nvic_writel()
2045 int excnum = (value & 0x1ff) + NVIC_FIRST_IRQ; in nvic_writel()
2069 value &= (R_V7M_FPCCR_LSPACT_MASK | in nvic_writel()
2079 value &= ~R_V7M_FPCCR_RES0_MASK; in nvic_writel()
2085 uint32_t lspen = FIELD_EX32(value, V7M_FPCCR, LSPEN); in nvic_writel()
2089 uint32_t cor = FIELD_EX32(value, V7M_FPCCR, CLRONRET); in nvic_writel()
2093 uint32_t hfrdy = FIELD_EX32(value, V7M_FPCCR, HFRDY); in nvic_writel()
2094 uint32_t bfrdy = FIELD_EX32(value, V7M_FPCCR, BFRDY); in nvic_writel()
2100 uint32_t monrdy = FIELD_EX32(value, V7M_FPCCR, MONRDY); in nvic_writel()
2108 value &= R_V7M_FPCCR_BANKED_MASK; in nvic_writel()
2109 cpu->env.v7m.fpccr[M_REG_NS] = value; in nvic_writel()
2111 fpccr_s = value; in nvic_writel()
2118 value &= ~7; in nvic_writel()
2119 cpu->env.v7m.fpcar[attrs.secure] = value; in nvic_writel()
2128 value &= mask; in nvic_writel()
2130 value |= 4 << FPCR_LTPSIZE_SHIFT; in nvic_writel()
2132 cpu->env.v7m.fpdscr[attrs.secure] = value; in nvic_writel()
2340 uint64_t value, unsigned size, in nvic_sysreg_write() argument
2348 trace_nvic_sysreg_write(addr, value, size); in nvic_sysreg_write()
2364 if (value & (1 << i) && in nvic_sysreg_write()
2387 if (value & (1 << i) && in nvic_sysreg_write()
2403 set_prio(s, startvec + i, false, (value >> (i * 8)) & 0xff); in nvic_sysreg_write()
2416 int newprio = extract32(value, i * 8, 8); in nvic_sysreg_write()
2433 value <<= ((offset - 0xd28) * 8); in nvic_sysreg_write()
2438 value &= ~R_V7M_CFSR_BFSR_MASK; in nvic_sysreg_write()
2441 s->cpu->env.v7m.cfsr[attrs.secure] &= ~value; in nvic_sysreg_write()
2446 s->cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK); in nvic_sysreg_write()
2451 nvic_writel(s, offset, value, attrs); in nvic_sysreg_write()