Lines Matching full:vectors
111 if (s->vectors[irq].active || in nvic_rettobase()
135 * vectors[] array. in nvic_isrpending()
142 if (s->vectors[irq].pending) { in nvic_isrpending()
258 vec = &s->vectors[i]; in nvic_recompute_state_secure()
310 VecInfo *vec = &s->vectors[i]; in nvic_recompute_state()
409 s->vectors[ARMV7M_EXCP_HARD].active) { in armv7m_nvic_neg_prio_requested()
413 if (s->vectors[ARMV7M_EXCP_NMI].active && in armv7m_nvic_neg_prio_requested()
446 s->vectors[irq].prio = prio; in set_prio()
465 return s->vectors[irq].prio; in get_prio()
515 vec = &s->vectors[irq]; in armv7m_nvic_clear_pending()
551 vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq]; in do_armv7m_nvic_set_pending()
640 vec = &s->vectors[irq]; in do_armv7m_nvic_set_pending()
697 vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq]; in armv7m_nvic_set_pending_lazyfp()
735 vec = &s->vectors[irq]; in armv7m_nvic_set_pending_lazyfp()
782 vec = &s->vectors[pending]; in armv7m_nvic_acknowledge_irq()
838 vec = &s->vectors[irq]; in armv7m_nvic_complete_irq()
875 vec = &s->vectors[ARMV7M_EXCP_HARD]; in armv7m_nvic_complete_irq()
881 vec = &s->vectors[ARMV7M_EXCP_NMI]; in armv7m_nvic_complete_irq()
936 vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq]; in armv7m_nvic_get_ready_status()
961 vec = &s->vectors[n]; in set_irq_level()
1069 if (s->vectors[ARMV7M_EXCP_SYSTICK].pending) { in nvic_readl()
1073 if (s->vectors[ARMV7M_EXCP_PENDSV].pending) { in nvic_readl()
1079 && s->vectors[ARMV7M_EXCP_NMI].pending) { in nvic_readl()
1164 if (s->vectors[ARMV7M_EXCP_SECURE].active) { in nvic_readl()
1167 if (s->vectors[ARMV7M_EXCP_SECURE].enabled) { in nvic_readl()
1170 if (s->vectors[ARMV7M_EXCP_SECURE].pending) { in nvic_readl()
1174 if (s->vectors[ARMV7M_EXCP_MEM].active) { in nvic_readl()
1179 if (s->vectors[ARMV7M_EXCP_HARD].active) { in nvic_readl()
1182 if (s->vectors[ARMV7M_EXCP_HARD].pending) { in nvic_readl()
1186 if (s->vectors[ARMV7M_EXCP_USAGE].active) { in nvic_readl()
1189 if (s->vectors[ARMV7M_EXCP_SVC].active) { in nvic_readl()
1192 if (s->vectors[ARMV7M_EXCP_PENDSV].active) { in nvic_readl()
1195 if (s->vectors[ARMV7M_EXCP_SYSTICK].active) { in nvic_readl()
1198 if (s->vectors[ARMV7M_EXCP_USAGE].pending) { in nvic_readl()
1201 if (s->vectors[ARMV7M_EXCP_MEM].pending) { in nvic_readl()
1204 if (s->vectors[ARMV7M_EXCP_SVC].pending) { in nvic_readl()
1207 if (s->vectors[ARMV7M_EXCP_MEM].enabled) { in nvic_readl()
1210 if (s->vectors[ARMV7M_EXCP_USAGE].enabled) { in nvic_readl()
1215 if (s->vectors[ARMV7M_EXCP_BUS].active) { in nvic_readl()
1218 if (s->vectors[ARMV7M_EXCP_BUS].pending) { in nvic_readl()
1221 if (s->vectors[ARMV7M_EXCP_BUS].enabled) { in nvic_readl()
1225 s->vectors[ARMV7M_EXCP_NMI].active) { in nvic_readl()
1232 if (s->vectors[ARMV7M_EXCP_DEBUG].active) { in nvic_readl()
1644 s->vectors[ARMV7M_EXCP_HARD].enabled = 1; in nvic_writel()
1647 s->vectors[ARMV7M_EXCP_HARD].enabled = 0; in nvic_writel()
1734 s->vectors[ARMV7M_EXCP_SECURE].active = (value & (1 << 4)) != 0; in nvic_writel()
1735 s->vectors[ARMV7M_EXCP_SECURE].enabled = (value & (1 << 19)) != 0; in nvic_writel()
1736 s->vectors[ARMV7M_EXCP_SECURE].pending = (value & (1 << 20)) != 0; in nvic_writel()
1738 s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0; in nvic_writel()
1741 s->vectors[ARMV7M_EXCP_HARD].pending = (value & (1 << 21)) != 0; in nvic_writel()
1743 s->vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0; in nvic_writel()
1744 s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0; in nvic_writel()
1745 s->vectors[ARMV7M_EXCP_PENDSV].active = (value & (1 << 10)) != 0; in nvic_writel()
1746 s->vectors[ARMV7M_EXCP_SYSTICK].active = (value & (1 << 11)) != 0; in nvic_writel()
1747 s->vectors[ARMV7M_EXCP_USAGE].pending = (value & (1 << 12)) != 0; in nvic_writel()
1748 s->vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0; in nvic_writel()
1749 s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0; in nvic_writel()
1750 s->vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0; in nvic_writel()
1751 s->vectors[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0; in nvic_writel()
1754 s->vectors[ARMV7M_EXCP_BUS].active = (value & (1 << 1)) != 0; in nvic_writel()
1755 s->vectors[ARMV7M_EXCP_BUS].pending = (value & (1 << 14)) != 0; in nvic_writel()
1756 s->vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0; in nvic_writel()
1764 s->vectors[ARMV7M_EXCP_NMI].active = 0; in nvic_writel()
1775 s->vectors[ARMV7M_EXCP_HARD].active = 0; in nvic_writel()
1779 s->vectors[ARMV7M_EXCP_DEBUG].active = (value & (1 << 8)) != 0; in nvic_writel()
2234 if (s->vectors[startvec + i].enabled && in nvic_sysreg_read()
2247 if (s->vectors[startvec + i].pending && in nvic_sysreg_read()
2263 if (s->vectors[startvec + i].active && in nvic_sysreg_read()
2275 val |= s->vectors[startvec + i].prio << (8 * i); in nvic_sysreg_read()
2366 s->vectors[startvec + i].enabled = setval; in nvic_sysreg_write()
2389 !(setval == 0 && s->vectors[startvec + i].level && in nvic_sysreg_write()
2390 !s->vectors[startvec + i].active)) { in nvic_sysreg_write()
2391 s->vectors[startvec + i].pending = setval; in nvic_sysreg_write()
2481 if (s->vectors[ARMV7M_EXCP_RESET].prio != resetprio || in nvic_post_load()
2482 s->vectors[ARMV7M_EXCP_NMI].prio != -2 || in nvic_post_load()
2483 s->vectors[ARMV7M_EXCP_HARD].prio != -1) { in nvic_post_load()
2487 if (s->vectors[i].prio & ~0xff) { in nvic_post_load()
2561 VMSTATE_STRUCT_ARRAY(vectors, NVICState, NVIC_MAX_VECTORS, 1,
2588 memset(s->vectors, 0, sizeof(s->vectors)); in armv7m_nvic_reset()
2593 s->vectors[ARMV7M_EXCP_NMI].enabled = 1; in armv7m_nvic_reset()
2597 s->vectors[ARMV7M_EXCP_SVC].enabled = 1; in armv7m_nvic_reset()
2598 s->vectors[ARMV7M_EXCP_PENDSV].enabled = 1; in armv7m_nvic_reset()
2599 s->vectors[ARMV7M_EXCP_SYSTICK].enabled = 1; in armv7m_nvic_reset()
2602 s->vectors[ARMV7M_EXCP_DEBUG].enabled = 0; in armv7m_nvic_reset()
2605 s->vectors[ARMV7M_EXCP_RESET].prio = resetprio; in armv7m_nvic_reset()
2606 s->vectors[ARMV7M_EXCP_NMI].prio = -2; in armv7m_nvic_reset()
2607 s->vectors[ARMV7M_EXCP_HARD].prio = -1; in armv7m_nvic_reset()
2618 s->vectors[ARMV7M_EXCP_HARD].enabled = 0; in armv7m_nvic_reset()
2620 s->vectors[ARMV7M_EXCP_HARD].enabled = 1; in armv7m_nvic_reset()
2690 /* include space for internal exception vectors */ in armv7m_nvic_realize()