Lines Matching full:secure
62 /* Maximum priority of non-secure exceptions when AIRCR.PRIS is set */
166 static inline uint32_t nvic_gprio_mask(NVICState *s, bool secure) in nvic_gprio_mask() argument
168 return ~0U << (s->prigroup[secure] + 1); in nvic_gprio_mask()
173 /* Return true if this non-banked exception targets Secure state. */ in exc_targets_secure()
208 * secure state or not. in exc_group_prio()
240 * - secure exception takes precedence in nvic_recompute_state_secure()
301 * would be even worse, so we retain a separate non-secure-only in nvic_recompute_state()
394 bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) in armv7m_nvic_neg_prio_requested() argument
404 if (s->cpu->env.v7m.faultmask[secure]) { in armv7m_nvic_neg_prio_requested()
408 if (secure ? s->sec_vectors[ARMV7M_EXCP_HARD].active : in armv7m_nvic_neg_prio_requested()
414 exc_targets_secure(s, ARMV7M_EXCP_NMI) == secure) { in armv7m_nvic_neg_prio_requested()
432 * secure indicates the bank to use for banked exceptions (we assert if
433 * we are passed secure=true for a non-banked exception).
435 static void set_prio(NVICState *s, unsigned irq, bool secure, uint8_t prio) in set_prio() argument
442 if (secure) { in set_prio()
449 trace_nvic_set_prio(irq, secure, prio); in set_prio()
453 * secure indicates the bank to use for banked exceptions (we assert if
454 * we are passed secure=true for a non-banked exception).
456 static int get_prio(NVICState *s, unsigned irq, bool secure) in get_prio() argument
461 if (secure) { in get_prio()
497 * @secure: false for non-banked exceptions or for the nonsecure
498 * version of a banked exception, true for the secure version of a banked
502 * if @secure is true and @irq does not specify one of the fixed set
505 static void armv7m_nvic_clear_pending(NVICState *s, int irq, bool secure) in armv7m_nvic_clear_pending() argument
511 if (secure) { in armv7m_nvic_clear_pending()
517 trace_nvic_clear_pending(irq, secure, vec->enabled, vec->prio); in armv7m_nvic_clear_pending()
524 static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure, in do_armv7m_nvic_set_pending() argument
549 assert(!secure || banked); in do_armv7m_nvic_set_pending()
551 vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq]; in do_armv7m_nvic_set_pending()
553 targets_secure = banked ? secure : exc_targets_secure(s, irq); in do_armv7m_nvic_set_pending()
555 trace_nvic_set_pending(irq, secure, targets_secure, in do_armv7m_nvic_set_pending()
563 exc_group_prio(s, vec->prio, secure) >= nvic_exec_prio(s)) { in do_armv7m_nvic_set_pending()
619 if (exc_group_prio(s, vec->prio, secure) >= running) { in do_armv7m_nvic_set_pending()
632 * we take a Secure HardFault. in do_armv7m_nvic_set_pending()
664 void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure) in armv7m_nvic_set_pending() argument
666 do_armv7m_nvic_set_pending(s, irq, secure, false); in armv7m_nvic_set_pending()
669 void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure) in armv7m_nvic_set_pending_derived() argument
671 do_armv7m_nvic_set_pending(s, irq, secure, true); in armv7m_nvic_set_pending_derived()
674 void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure) in armv7m_nvic_set_pending_lazyfp() argument
688 * (in which case 'secure' tells us whether it is the S or NS version). in armv7m_nvic_set_pending_lazyfp()
692 uint32_t fpccr = s->cpu->env.v7m.fpccr[secure]; in armv7m_nvic_set_pending_lazyfp()
695 assert(!secure || banked); in armv7m_nvic_set_pending_lazyfp()
697 vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq]; in armv7m_nvic_set_pending_lazyfp()
699 targets_secure = banked ? secure : exc_targets_secure(s, irq); in armv7m_nvic_set_pending_lazyfp()
726 * Escalate to HardFault: faults that initially targeted Secure in armv7m_nvic_set_pending_lazyfp()
740 nvic_exec_prio(s) <= exc_group_prio(s, vec->prio, secure)) { in armv7m_nvic_set_pending_lazyfp()
802 /* Return true if s->vectpending targets Secure state */ in vectpending_targets_secure()
826 int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure) in armv7m_nvic_complete_irq() argument
833 trace_nvic_complete_irq(irq, secure); in armv7m_nvic_complete_irq()
835 if (secure && exc_is_banked(irq)) { in armv7m_nvic_complete_irq()
846 if (!exc_is_banked(irq) && exc_targets_secure(s, irq) != secure) { in armv7m_nvic_complete_irq()
909 bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure) in armv7m_nvic_get_ready_status() argument
916 * irq and secure have the same semantics as for armv7m_nvic_set_pending(): in armv7m_nvic_get_ready_status()
917 * for non-banked exceptions secure is always false; for banked exceptions in armv7m_nvic_get_ready_status()
925 assert(!secure || banked); in armv7m_nvic_get_ready_status()
929 * even if we're secure and HardFault has priority -3; we never in armv7m_nvic_get_ready_status()
936 vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq]; in armv7m_nvic_get_ready_status()
939 exc_group_prio(s, vec->prio, secure) < running; in armv7m_nvic_get_ready_status()
1015 if (!attrs.secure) { in nvic_readl()
1041 * exception targets Secure. in nvic_readl()
1044 if (!attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_V8_1M) && in nvic_readl()
1058 if (attrs.secure) { in nvic_readl()
1078 if ((attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) in nvic_readl()
1086 return cpu->env.v7m.vecbase[attrs.secure]; in nvic_readl()
1088 val = 0xfa050000 | (s->prigroup[attrs.secure] << 8); in nvic_readl()
1089 if (attrs.secure) { in nvic_readl()
1106 return cpu->env.v7m.scr[attrs.secure]; in nvic_readl()
1112 val = cpu->env.v7m.ccr[attrs.secure]; in nvic_readl()
1115 if (!attrs.secure) { in nvic_readl()
1126 if (attrs.secure) { in nvic_readl()
1214 if (attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { in nvic_readl()
1247 return cpu->env.v7m.mmfar[attrs.secure]; in nvic_readl()
1252 if (!attrs.secure && in nvic_readl()
1338 int idx = cpu->env.v7m.csselr[attrs.secure] & R_V7M_CSSELR_INDEX_MASK; in nvic_readl()
1342 return cpu->env.v7m.csselr[attrs.secure]; in nvic_readl()
1347 return cpu->env.v7m.cpacr[attrs.secure]; in nvic_readl()
1349 if (!attrs.secure || !cpu_isar_feature(aa32_vfp_simd, cpu)) { in nvic_readl()
1358 return cpu->env.v7m.mpu_ctrl[attrs.secure]; in nvic_readl()
1360 return cpu->env.pmsav7.rnr[attrs.secure]; in nvic_readl()
1366 int region = cpu->env.pmsav7.rnr[attrs.secure]; in nvic_readl()
1381 return cpu->env.pmsav8.rbar[attrs.secure][region]; in nvic_readl()
1394 int region = cpu->env.pmsav7.rnr[attrs.secure]; in nvic_readl()
1408 return cpu->env.pmsav8.rlar[attrs.secure][region]; in nvic_readl()
1421 return cpu->env.pmsav8.mair0[attrs.secure]; in nvic_readl()
1426 return cpu->env.pmsav8.mair1[attrs.secure]; in nvic_readl()
1431 if (!attrs.secure) { in nvic_readl()
1439 if (!attrs.secure) { in nvic_readl()
1447 if (!attrs.secure) { in nvic_readl()
1458 if (!attrs.secure) { in nvic_readl()
1473 if (!attrs.secure) { in nvic_readl()
1485 if (!attrs.secure) { in nvic_readl()
1493 if (!attrs.secure) { in nvic_readl()
1507 if (attrs.secure) { in nvic_readl()
1534 return cpu->env.v7m.fpcar[attrs.secure]; in nvic_readl()
1539 return cpu->env.v7m.fpdscr[attrs.secure]; in nvic_readl()
1573 if (!attrs.secure) { in nvic_writel()
1583 if (attrs.secure || cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { in nvic_writel()
1593 armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure); in nvic_writel()
1595 armv7m_nvic_clear_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure); in nvic_writel()
1598 armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, attrs.secure); in nvic_writel()
1600 armv7m_nvic_clear_pending(s, ARMV7M_EXCP_SYSTICK, attrs.secure); in nvic_writel()
1604 cpu->env.v7m.vecbase[attrs.secure] = value & 0xffffff80; in nvic_writel()
1609 if (attrs.secure || in nvic_writel()
1626 s->prigroup[attrs.secure] = in nvic_writel()
1632 if (attrs.secure) { in nvic_writel()
1633 /* These bits are only writable by secure */ in nvic_writel()
1638 /* BFHFNMINS changes the priority of Secure HardFault, and in nvic_writel()
1639 * allows a pending Non-secure HardFault to preempt (which in nvic_writel()
1663 cpu->env.v7m.scr[attrs.secure] = value; in nvic_writel()
1680 if (arm_feature(&cpu->env, ARM_FEATURE_V8_1M) && attrs.secure) { in nvic_writel()
1691 if (attrs.secure) { in nvic_writel()
1708 cpu->env.v7m.ccr[attrs.secure] = value; in nvic_writel()
1715 if (attrs.secure) { in nvic_writel()
1717 /* Secure HardFault active bit cannot be written */ in nvic_writel()
1753 if (attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { in nvic_writel()
1759 * BFHFNMINS 1, and by the CPU in secure state via the NS alias. in nvic_writel()
1761 if (!attrs.secure && cpu->env.v7m.secure && in nvic_writel()
1767 * to the non-secure HardFault state by the CPU in secure state. in nvic_writel()
1768 * The only case where we can be targeting the non-secure HF state in nvic_writel()
1769 * when in secure state is if this is a write via the NS alias in nvic_writel()
1772 if (!attrs.secure && cpu->env.v7m.secure && in nvic_writel()
1795 cpu->env.v7m.mmfar[attrs.secure] = value; in nvic_writel()
1801 if (!attrs.secure && in nvic_writel()
1813 cpu->env.v7m.csselr[attrs.secure] = value & R_V7M_CSSELR_INDEX_MASK; in nvic_writel()
1819 cpu->env.v7m.cpacr[attrs.secure] = value & (0xf << 20); in nvic_writel()
1823 if (attrs.secure && cpu_isar_feature(aa32_vfp_simd, cpu)) { in nvic_writel()
1837 cpu->env.v7m.mpu_ctrl[attrs.secure] in nvic_writel()
1849 cpu->env.pmsav7.rnr[attrs.secure] = value; in nvic_writel()
1867 region = cpu->env.pmsav7.rnr[attrs.secure]; in nvic_writel()
1874 cpu->env.pmsav8.rbar[attrs.secure][region] = value; in nvic_writel()
1890 cpu->env.pmsav7.rnr[attrs.secure] = region; in nvic_writel()
1892 region = cpu->env.pmsav7.rnr[attrs.secure]; in nvic_writel()
1908 int region = cpu->env.pmsav7.rnr[attrs.secure]; in nvic_writel()
1917 region = cpu->env.pmsav7.rnr[attrs.secure]; in nvic_writel()
1924 cpu->env.pmsav8.rlar[attrs.secure][region] = value; in nvic_writel()
1944 cpu->env.pmsav8.mair0[attrs.secure] = value; in nvic_writel()
1956 cpu->env.pmsav8.mair1[attrs.secure] = value; in nvic_writel()
1966 if (!attrs.secure) { in nvic_writel()
1980 if (!attrs.secure) { in nvic_writel()
1998 if (!attrs.secure) { in nvic_writel()
2015 if (!attrs.secure) { in nvic_writel()
2029 if (!attrs.secure) { in nvic_writel()
2038 if (!attrs.secure) { in nvic_writel()
2081 if (!attrs.secure) { in nvic_writel()
2119 cpu->env.v7m.fpcar[attrs.secure] = value; in nvic_writel()
2132 cpu->env.v7m.fpdscr[attrs.secure] = value; in nvic_writel()
2160 * controls access even though the CPU is in Secure state (I_QDKX). in nvic_user_access_ok()
2162 return s->cpu->env.v7m.ccr[attrs.secure] & R_V7M_CCR_USERSETMPEND_MASK; in nvic_user_access_ok()
2173 * non-banked exceptions), M_REG_S for the secure version of in shpr_bank()
2183 return attrs.secure; in shpr_bank()
2186 if (!attrs.secure && in shpr_bank()
2193 if (!attrs.secure) { in shpr_bank()
2235 (attrs.secure || s->itns[startvec + i])) { in nvic_sysreg_read()
2248 (attrs.secure || s->itns[startvec + i])) { in nvic_sysreg_read()
2264 (attrs.secure || s->itns[startvec + i])) { in nvic_sysreg_read()
2274 if (attrs.secure || s->itns[startvec + i]) { in nvic_sysreg_read()
2307 val = s->cpu->env.v7m.cfsr[attrs.secure]; in nvic_sysreg_read()
2308 if (!attrs.secure && in nvic_sysreg_read()
2365 (attrs.secure || s->itns[startvec + i])) { in nvic_sysreg_write()
2388 (attrs.secure || s->itns[startvec + i]) && in nvic_sysreg_write()
2402 if (attrs.secure || s->itns[startvec + i]) { in nvic_sysreg_write()
2435 if (!attrs.secure && in nvic_sysreg_write()
2441 s->cpu->env.v7m.cfsr[attrs.secure] &= ~value; in nvic_sysreg_write()
2442 if (attrs.secure) { in nvic_sysreg_write()
2615 /* AIRCR.BFHFNMINS resets to 0 so Secure HF is priority -1 (R_CMTC) */ in armv7m_nvic_reset()
2667 * n == 1 : Secure systick in nvic_systick_trigger()