85     /* return the group priority of the current pending interrupt,  in nvic_pending_prio()
86      * or NVIC_NOEXC_PRIO if no interrupt is pending  in nvic_pending_prio()
125  * 1 if an external interrupt is pending
126  * 0 if no external interrupt is pending
133      * We can shortcut if the highest priority pending interrupt  in nvic_isrpending()
142         if (s->vectors[irq].pending) {  in nvic_isrpending()
264             if (vec->enabled && vec->pending &&  in nvic_recompute_state_secure()
312         if (vec->enabled && vec->pending && vec->prio < pend_prio) {  in nvic_recompute_state()
471  *  vec->active, vec->enabled, vec->pending or vec->prio for any vector
486      * pending info.  in nvic_irq_update()
494  * armv7m_nvic_clear_pending: mark the specified exception as not pending
496  * @irq: the exception number to mark as not pending
501  * Marks the specified exception as not pending. Note that we will assert()
518     if (vec->pending) {  in armv7m_nvic_clear_pending()
519         vec->pending = 0;  in armv7m_nvic_clear_pending()
529      * This function handles both "normal" pending of interrupts and  in do_armv7m_nvic_set_pending()
587         /* We now continue with the same code as for a normal pending  in do_armv7m_nvic_set_pending()
591          * for selecting the highest priority pending interrupt.  in do_armv7m_nvic_set_pending()
596         /* If a synchronous exception is pending then it may be  in do_armv7m_nvic_set_pending()
601          * Asynchronous exceptions (and interrupts) simply remain pending.  in do_armv7m_nvic_set_pending()
658     if (!vec->pending) {  in do_armv7m_nvic_set_pending()
659         vec->pending = 1;  in do_armv7m_nvic_set_pending()
678      * from the usual exception pending because the logic for  in armv7m_nvic_set_pending_lazyfp()
755     if (!vec->pending) {  in armv7m_nvic_set_pending_lazyfp()
756         vec->pending = 1;  in armv7m_nvic_set_pending_lazyfp()
769 /* Make pending IRQ active.  */
773     const int pending = s->vectpending;  in armv7m_nvic_acknowledge_irq()  local
777     assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);  in armv7m_nvic_acknowledge_irq()
780         vec = &s->sec_vectors[pending];  in armv7m_nvic_acknowledge_irq()
782         vec = &s->vectors[pending];  in armv7m_nvic_acknowledge_irq()
786     assert(vec->pending);  in armv7m_nvic_acknowledge_irq()
790     trace_nvic_acknowledge_irq(pending, s->vectpending_prio);  in armv7m_nvic_acknowledge_irq()
793     vec->pending = 0;  in armv7m_nvic_acknowledge_irq()
813     const int pending = s->vectpending;  in armv7m_nvic_get_pending_irq_info()  local
816     assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);  in armv7m_nvic_get_pending_irq_info()
820     trace_nvic_get_pending_irq_info(pending, targets_secure);  in armv7m_nvic_get_pending_irq_info()
823     *pirq = pending;  in armv7m_nvic_get_pending_irq_info()
901         vec->pending = 1;  in armv7m_nvic_complete_irq()
954     /* The pending status of an external interrupt is  in set_irq_level()
981      * set NMI pending here and don't track the current level.  in nvic_nmi_trigger()
1041              * NonSecure and the highest priority pending and enabled  in nvic_readl()
1051         /* ISRPENDING - set if any external IRQ is pending */  in nvic_readl()
1061             if (s->sec_vectors[ARMV7M_EXCP_SYSTICK].pending) {  in nvic_readl()
1065             if (s->sec_vectors[ARMV7M_EXCP_PENDSV].pending) {  in nvic_readl()
1070             if (s->vectors[ARMV7M_EXCP_SYSTICK].pending) {  in nvic_readl()
1074             if (s->vectors[ARMV7M_EXCP_PENDSV].pending) {  in nvic_readl()
1080             && s->vectors[ARMV7M_EXCP_NMI].pending) {  in nvic_readl()
1146             if (s->sec_vectors[ARMV7M_EXCP_USAGE].pending) {  in nvic_readl()
1149             if (s->sec_vectors[ARMV7M_EXCP_MEM].pending) {  in nvic_readl()
1152             if (s->sec_vectors[ARMV7M_EXCP_SVC].pending) {  in nvic_readl()
1161             if (s->sec_vectors[ARMV7M_EXCP_HARD].pending) {  in nvic_readl()
1171             if (s->vectors[ARMV7M_EXCP_SECURE].pending) {  in nvic_readl()
1183                 if (s->vectors[ARMV7M_EXCP_HARD].pending) {  in nvic_readl()
1199             if (s->vectors[ARMV7M_EXCP_USAGE].pending) {  in nvic_readl()
1202             if (s->vectors[ARMV7M_EXCP_MEM].pending) {  in nvic_readl()
1205             if (s->vectors[ARMV7M_EXCP_SVC].pending) {  in nvic_readl()
1219             if (s->vectors[ARMV7M_EXCP_BUS].pending) {  in nvic_readl()
1640                  * allows a pending Non-secure HardFault to preempt (which  in nvic_writel()
1725             s->sec_vectors[ARMV7M_EXCP_USAGE].pending =  in nvic_writel()
1727             s->sec_vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;  in nvic_writel()
1728             s->sec_vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;  in nvic_writel()
1733             s->sec_vectors[ARMV7M_EXCP_HARD].pending = (value & (1 << 21)) != 0;  in nvic_writel()
1737             s->vectors[ARMV7M_EXCP_SECURE].pending = (value & (1 << 20)) != 0;  in nvic_writel()
1742                 s->vectors[ARMV7M_EXCP_HARD].pending = (value & (1 << 21)) != 0;  in nvic_writel()
1748             s->vectors[ARMV7M_EXCP_USAGE].pending = (value & (1 << 12)) != 0;  in nvic_writel()
1749             s->vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;  in nvic_writel()
1750             s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;  in nvic_writel()
1756             s->vectors[ARMV7M_EXCP_BUS].pending = (value & (1 << 14)) != 0;  in nvic_writel()
2248             if (s->vectors[startvec + i].pending &&  in nvic_sysreg_read()
2385              * is not active then rule R_CVJS requires that the Pending state  in nvic_sysreg_write()
2392                 s->vectors[startvec + i].pending = setval;  in nvic_sysreg_write()
2505         VMSTATE_UINT8(pending, VecInfo),