Lines Matching +full:secure +full:- +full:only
19 * Secure interrupts:
20 * 0b00: no access (NS accesses to bits for Secure interrupts will RAZ/WI)
26 * Given a (multiple-of-32) interrupt number, these mask functions return
37 uint64_t raw_nsacr = s->gicd_nsacr[irq / 16 + 1]; in mask_nsacr_ge1()
39 raw_nsacr = raw_nsacr << 32 | s->gicd_nsacr[irq / 16]; in mask_nsacr_ge1()
47 uint64_t raw_nsacr = s->gicd_nsacr[irq / 16 + 1]; in mask_nsacr_ge2()
49 raw_nsacr = raw_nsacr << 32 | s->gicd_nsacr[irq / 16]; in mask_nsacr_ge2()
62 /* Return a 32-bit mask which should be applied for this set of 32 in mask_group_and_nsacr()
64 * combination of attrs.secure, GICD_GROUPR and GICD_NSACR. in mask_group_and_nsacr()
68 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { in mask_group_and_nsacr()
69 /* bits for Group 0 or Secure Group 1 interrupts are RAZ/WI in mask_group_and_nsacr()
72 mask = *gic_bmp_ptr32(s->group, irq); in mask_group_and_nsacr()
86 if (irq < GIC_INTERNAL || irq >= s->num_irq) { in gicd_ns_access()
89 return extract32(s->gicd_nsacr[irq / 16], (irq % 16) * 2, 2); in gicd_ns_access()
101 * Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI. in gicd_write_bitmap_reg()
107 if (irq < GIC_INTERNAL || irq >= s->num_irq) { in gicd_write_bitmap_reg()
120 /* Helper routine to implement writing to a "set-bitmap" register in gicd_write_set_bitmap_reg()
124 * Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI. in gicd_write_set_bitmap_reg()
131 if (irq < GIC_INTERNAL || irq >= s->num_irq) { in gicd_write_set_bitmap_reg()
144 /* Helper routine to implement writing to a "clear-bitmap" register in gicd_write_clear_bitmap_reg()
148 * Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI. in gicd_write_clear_bitmap_reg()
155 if (irq < GIC_INTERNAL || irq >= s->num_irq) { in gicd_write_clear_bitmap_reg()
168 /* Helper routine to implement reading a "set/clear-bitmap" register in gicd_read_bitmap_reg()
172 * Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI. in gicd_read_bitmap_reg()
179 if (irq < GIC_INTERNAL || irq >= s->num_irq) { in gicd_read_bitmap_reg()
183 if (bmp == s->pending) { in gicd_read_bitmap_reg()
184 /* The PENDING register is a special case -- for level triggered in gicd_read_bitmap_reg()
188 uint32_t edge = *gic_bmp_ptr32(s->edge_trigger, irq); in gicd_read_bitmap_reg()
189 uint32_t level = *gic_bmp_ptr32(s->level, irq); in gicd_read_bitmap_reg()
199 * honouring security state (these are RAZ/WI for Group 0 or Secure in gicd_read_ipriorityr()
204 if (irq < GIC_INTERNAL || irq >= s->num_irq) { in gicd_read_ipriorityr()
208 prio = s->gicd_ipriority[irq]; in gicd_read_ipriorityr()
210 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { in gicd_read_ipriorityr()
212 /* Fields for Group 0 or Secure Group 1 interrupts are RAZ/WI */ in gicd_read_ipriorityr()
225 * honouring security state (these are RAZ/WI for Group 0 or Secure in gicd_write_ipriorityr()
228 if (irq < GIC_INTERNAL || irq >= s->num_irq) { in gicd_write_ipriorityr()
232 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { in gicd_write_ipriorityr()
234 /* Fields for Group 0 or Secure Group 1 interrupts are RAZ/WI */ in gicd_write_ipriorityr()
240 s->gicd_ipriority[irq] = value; in gicd_write_ipriorityr()
248 if (irq < GIC_INTERNAL || irq >= s->num_irq) { in gicd_read_irouter()
252 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { in gicd_read_irouter()
253 /* RAZ/WI for NS accesses to secure interrupts */ in gicd_read_irouter()
261 return s->gicd_irouter[irq]; in gicd_read_irouter()
270 if (irq < GIC_INTERNAL || irq >= s->num_irq) { in gicd_write_irouter()
274 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { in gicd_write_irouter()
275 /* RAZ/WI for NS accesses to secure interrupts */ in gicd_write_irouter()
283 s->gicd_irouter[irq] = val; in gicd_write_irouter()
314 *data = gicd_read_ipriorityr(s, attrs, offset - GICD_IPRIORITYR); in gicd_readb()
335 int irq = offset - GICD_IPRIORITYR; in gicd_writeb()
337 if (irq < GIC_INTERNAL || irq >= s->num_irq) { in gicd_writeb()
352 /* Only GICD_SETSPI_NSR, GICD_CLRSPI_NSR, GICD_SETSPI_SR and GICD_SETSPI_NSR in gicd_readw()
354 * optional message-based SPI feature which this GIC does not currently in gicd_readw()
364 /* Only GICD_SETSPI_NSR, GICD_CLRSPI_NSR, GICD_SETSPI_SR and GICD_SETSPI_NSR in gicd_writew()
366 * optional message-based SPI feature which this GIC does not currently in gicd_writew()
376 /* Almost all GICv3 distributor registers are 32-bit. in gicd_readl()
383 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { in gicd_readl()
384 /* The NS view of the GICD_CTLR sees only certain bits: in gicd_readl()
385 * + bit [31] (RWP) is an alias of the Secure bit [31] in gicd_readl()
386 * + bit [4] (ARE_NS) is an alias of Secure bit [5] in gicd_readl()
387 * + bit [1] (EnableGrp1A) is an alias of Secure bit [1] if in gicd_readl()
389 * + bit [0] (EnableGrp1) is an alias of Secure bit [1] if in gicd_readl()
396 *data = s->gicd_ctlr & (GICD_CTLR_ARE_S | in gicd_readl()
400 *data = s->gicd_ctlr; in gicd_readl()
406 * No1N == 1 (1-of-N SPI interrupts not supported) in gicd_readl()
407 * A3V == 1 (non-zero values of Affinity level 3 supported) in gicd_readl()
408 * IDbits == 0xf (we support 16-bit interrupt identifiers) in gicd_readl()
413 * MBIS == 0 (message-based SPIs not supported) in gicd_readl()
415 * NMI = 1 if Non-maskable interrupt property is supported in gicd_readl()
417 * ITLinesNumber == (((max SPI IntID + 1) / 32) - 1) in gicd_readl()
419 int itlinesnumber = (s->num_irq / 32) - 1; in gicd_readl()
423 * so we only need to check the DS bit. in gicd_readl()
425 bool sec_extn = !(s->gicd_ctlr & GICD_CTLR_DS); in gicd_readl()
426 bool dvis = s->revision >= 4; in gicd_readl()
429 (s->nmi_support << GICD_TYPER_NMI_SHIFT) | in gicd_readl()
430 (s->lpi_enable << GICD_TYPER_LPIS_SHIFT) | in gicd_readl()
436 * This is the same as an r0p0 GIC-500. in gicd_readl()
450 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { in gicd_readl()
455 irq = (offset - GICD_IGROUPR) * 8; in gicd_readl()
456 if (irq < GIC_INTERNAL || irq >= s->num_irq) { in gicd_readl()
460 *data = *gic_bmp_ptr32(s->group, irq); in gicd_readl()
464 *data = gicd_read_bitmap_reg(s, attrs, s->enabled, NULL, in gicd_readl()
465 offset - GICD_ISENABLER); in gicd_readl()
468 *data = gicd_read_bitmap_reg(s, attrs, s->enabled, NULL, in gicd_readl()
469 offset - GICD_ICENABLER); in gicd_readl()
472 *data = gicd_read_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge1, in gicd_readl()
473 offset - GICD_ISPENDR); in gicd_readl()
476 *data = gicd_read_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge2, in gicd_readl()
477 offset - GICD_ICPENDR); in gicd_readl()
480 *data = gicd_read_bitmap_reg(s, attrs, s->active, mask_nsacr_ge2, in gicd_readl()
481 offset - GICD_ISACTIVER); in gicd_readl()
484 *data = gicd_read_bitmap_reg(s, attrs, s->active, mask_nsacr_ge2, in gicd_readl()
485 offset - GICD_ICACTIVER); in gicd_readl()
489 int i, irq = offset - GICD_IPRIORITYR; in gicd_readl()
492 for (i = irq + 3; i >= irq; i--) { in gicd_readl()
505 /* Here only the even bits are used; odd bits are RES0 */ in gicd_readl()
506 int irq = (offset - GICD_ICFGR) * 4; in gicd_readl()
509 if (irq < GIC_INTERNAL || irq >= s->num_irq) { in gicd_readl()
514 /* Since our edge_trigger bitmap is one bit per irq, we only need in gicd_readl()
515 * half of the 32-bit word, which we can then spread out in gicd_readl()
518 value = *gic_bmp_ptr32(s->edge_trigger, irq & ~0x1f); in gicd_readl()
529 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { in gicd_readl()
537 irq = (offset - GICD_IGRPMODR) * 8; in gicd_readl()
538 if (irq < GIC_INTERNAL || irq >= s->num_irq) { in gicd_readl()
542 *data = *gic_bmp_ptr32(s->grpmod, irq); in gicd_readl()
548 int irq = (offset - GICD_NSACR) * 4; in gicd_readl()
550 if (irq < GIC_INTERNAL || irq >= s->num_irq) { in gicd_readl()
555 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { in gicd_readl()
563 *data = s->gicd_nsacr[irq / 16]; in gicd_readl()
572 *data = (!s->nmi_support) ? 0 : in gicd_readl()
573 gicd_read_bitmap_reg(s, attrs, s->nmi, NULL, in gicd_readl()
574 offset - GICD_INMIR); in gicd_readl()
579 int irq = (offset - GICD_IROUTER) / 8; in gicd_readl()
591 *data = gicv3_idreg(s, offset - GICD_IDREGS, GICV3_PIDR0_DIST); in gicd_readl()
608 /* Almost all GICv3 distributor registers are 32-bit. Note that in gicd_writel()
617 if (s->gicd_ctlr & GICD_CTLR_DS) { in gicd_writel()
618 /* With only one security state, E1NWF is RAZ/WI, DS is RAO/WI, in gicd_writel()
619 * ARE is RAO/WI (affinity routing always on), and only in gicd_writel()
624 if (attrs.secure) { in gicd_writel()
625 /* for secure access: in gicd_writel()
627 * E1NWF is RAZ/WI (we don't support enable-1-of-n-wakeup) in gicd_writel()
629 * We can only modify bits[2:0] (the group enables). in gicd_writel()
633 /* For non secure access ARE_NS is RAO/WI and EnableGrp1 in gicd_writel()
634 * is RES0. The only writable bit is [1] (EnableGrp1A), which in gicd_writel()
635 * is an alias of the Secure bit [1]. in gicd_writel()
640 s->gicd_ctlr = (s->gicd_ctlr & ~mask) | (value & mask); in gicd_writel()
643 * Note that this is a one-way transition because if DS is set in gicd_writel()
644 * then it's not writable, so it can only go back to 0 with a in gicd_writel()
647 s->gicd_ctlr &= ~(GICD_CTLR_EN_GRP1S | GICD_CTLR_ARE_NS); in gicd_writel()
659 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) { in gicd_writel()
663 irq = (offset - GICD_IGROUPR) * 8; in gicd_writel()
664 if (irq < GIC_INTERNAL || irq >= s->num_irq) { in gicd_writel()
667 *gic_bmp_ptr32(s->group, irq) = value; in gicd_writel()
672 gicd_write_set_bitmap_reg(s, attrs, s->enabled, NULL, in gicd_writel()
673 offset - GICD_ISENABLER, value); in gicd_writel()
676 gicd_write_clear_bitmap_reg(s, attrs, s->enabled, NULL, in gicd_writel()
677 offset - GICD_ICENABLER, value); in gicd_writel()
680 gicd_write_set_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge1, in gicd_writel()
681 offset - GICD_ISPENDR, value); in gicd_writel()
684 gicd_write_clear_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge2, in gicd_writel()
685 offset - GICD_ICPENDR, value); in gicd_writel()
688 gicd_write_set_bitmap_reg(s, attrs, s->active, NULL, in gicd_writel()
689 offset - GICD_ISACTIVER, value); in gicd_writel()
692 gicd_write_clear_bitmap_reg(s, attrs, s->active, NULL, in gicd_writel()
693 offset - GICD_ICACTIVER, value); in gicd_writel()
697 int i, irq = offset - GICD_IPRIORITYR; in gicd_writel()
699 if (irq < GIC_INTERNAL || irq + 3 >= s->num_irq) { in gicd_writel()
714 /* Here only the odd bits are used; even bits are RES0 */ in gicd_writel()
715 int irq = (offset - GICD_ICFGR) * 4; in gicd_writel()
718 if (irq < GIC_INTERNAL || irq >= s->num_irq) { in gicd_writel()
723 * 32-bits will compress down into 16 bits which we need in gicd_writel()
734 oldval = *gic_bmp_ptr32(s->edge_trigger, (irq & ~0x1f)); in gicd_writel()
736 *gic_bmp_ptr32(s->edge_trigger, irq & ~0x1f) = value; in gicd_writel()
743 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { in gicd_writel()
750 irq = (offset - GICD_IGRPMODR) * 8; in gicd_writel()
751 if (irq < GIC_INTERNAL || irq >= s->num_irq) { in gicd_writel()
754 *gic_bmp_ptr32(s->grpmod, irq) = value; in gicd_writel()
761 int irq = (offset - GICD_NSACR) * 4; in gicd_writel()
763 if (irq < GIC_INTERNAL || irq >= s->num_irq) { in gicd_writel()
767 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { in gicd_writel()
774 s->gicd_nsacr[irq / 16] = value; in gicd_writel()
775 /* No update required as this only affects access permission checks */ in gicd_writel()
786 if (s->nmi_support) { in gicd_writel()
787 gicd_write_bitmap_reg(s, attrs, s->nmi, NULL, in gicd_writel()
788 offset - GICD_INMIR, value); in gicd_writel()
794 int irq = (offset - GICD_IROUTER) / 8; in gicd_writel()
796 if (irq < GIC_INTERNAL || irq >= s->num_irq) { in gicd_writel()
800 /* Write half of the 64-bit register */ in gicd_writel()
822 /* Our only 64-bit registers are GICD_IROUTER<n> */ in gicd_writeq()
827 irq = (offset - GICD_IROUTER) / 8; in gicd_writeq()
838 /* Our only 64-bit registers are GICD_IROUTER<n> */ in gicd_readq()
843 irq = (offset - GICD_IROUTER) / 8; in gicd_readq()
879 trace_gicv3_dist_badread(offset, size, attrs.secure); in gicv3_dist_read()
882 * trigger the guest-error logging but don't return it to in gicv3_dist_read()
887 trace_gicv3_dist_read(offset, *data, size, attrs.secure); in gicv3_dist_read()
920 trace_gicv3_dist_badwrite(offset, data, size, attrs.secure); in gicv3_dist_write()
923 * trigger the guest-error logging but don't return it to in gicv3_dist_write()
927 trace_gicv3_dist_write(offset, data, size, attrs.secure); in gicv3_dist_write()
944 /* 0->1 edges latch the pending bit for edge-triggered interrupts */ in gicv3_dist_set_irq()