28      * pending interrupt for this CPU. We also return true if  in irqbetter()
29      * the current recorded highest priority pending interrupt  in irqbetter()
45     /* If multiple pending interrupts have the same priority then it is an  in irqbetter()
57     /* Recalculate which distributor interrupts are actually pending  in gicd_int_pending()
62      * An interrupt is pending if:  in gicd_int_pending()
63      *  + the PENDING latch is set OR it is level triggered and the input is 1  in gicd_int_pending()
66      *  + its ACTIVE bit is not set (otherwise it would be Active+Pending)  in gicd_int_pending()
70     uint32_t pending = *gic_bmp_ptr32(s->pending, irq);  in gicd_int_pending()  local
78     pend = pending | (~edge_trigger & level);  in gicd_int_pending()
103     /* Recalculate which redistributor interrupts are actually pending,  in gicr_int_pending()
107      * An interrupt is pending if:  in gicr_int_pending()
108      *  + the PENDING latch is set OR it is level triggered and the input is 1  in gicr_int_pending()
111      *  + its ACTIVE bit is not set (otherwise it would be Active+Pending)  in gicr_int_pending()
180     /* Find the highest priority pending interrupt among the  in gicv3_redist_update_noirqset()
230      * previous pending interrupt at all), then that is still valid, and  in gicv3_redist_update_noirqset()
245  * its new highest priority pending interrupt.
271     /* Find the highest priority pending interrupt in this range. */  in gicv3_update_noirqset()
276             /* Calculate the next 32 bits worth of pending status */  in gicv3_update_noirqset()
285             /* Interrupts targeting no implemented CPU should remain pending  in gicv3_update_noirqset()
304      * no previous pending interrupt at all), then that  in gicv3_update_noirqset()
406      * pending interrupt, but don't set IRQ or FIQ lines.  in arm_gicv3_post_load()