44     SiI3112PCIState *d = opaque;  in sii3112_reg_read()  local
49         val = d->i.bmdma[0].cmd;  in sii3112_reg_read()
52         val = d->regs[0].swdata;  in sii3112_reg_read()
55         val = d->i.bmdma[0].status;  in sii3112_reg_read()
61         val = bmdma_addr_ioport_ops.read(&d->i.bmdma[0], addr - 4, size);  in sii3112_reg_read()
64         val = d->i.bmdma[1].cmd;  in sii3112_reg_read()
67         val = d->regs[1].swdata;  in sii3112_reg_read()
70         val = d->i.bmdma[1].status;  in sii3112_reg_read()
76         val = bmdma_addr_ioport_ops.read(&d->i.bmdma[1], addr - 12, size);  in sii3112_reg_read()
79         val = d->i.bmdma[0].cmd;  in sii3112_reg_read()
80         val |= (d->regs[0].confstat & (1UL << 11) ? (1 << 4) : 0); /*SATAINT0*/  in sii3112_reg_read()
81         val |= (d->regs[1].confstat & (1UL << 11) ? (1 << 6) : 0); /*SATAINT1*/  in sii3112_reg_read()
82         val |= (d->i.bmdma[1].status & BM_STATUS_INT ? (1 << 14) : 0);  in sii3112_reg_read()
83         val |= (uint32_t)d->i.bmdma[0].status << 16;  in sii3112_reg_read()
84         val |= (uint32_t)d->i.bmdma[1].status << 24;  in sii3112_reg_read()
87         val = d->i.bmdma[1].cmd;  in sii3112_reg_read()
88         val |= (d->regs[1].confstat & (1UL << 11) ? (1 << 4) : 0);  in sii3112_reg_read()
89         val |= (uint32_t)d->i.bmdma[1].status << 16;  in sii3112_reg_read()
92         val = pci_ide_data_le_ops.read(&d->i.bus[0], addr - 0x80, size);  in sii3112_reg_read()
95         val = pci_ide_cmd_le_ops.read(&d->i.bus[0], 2, size);  in sii3112_reg_read()
98         val = d->regs[0].confstat;  in sii3112_reg_read()
101         val = pci_ide_data_le_ops.read(&d->i.bus[1], addr - 0xc0, size);  in sii3112_reg_read()
104         val = pci_ide_cmd_le_ops.read(&d->i.bus[1], 2, size);  in sii3112_reg_read()
107         val = d->regs[1].confstat;  in sii3112_reg_read()
110         val = d->regs[0].scontrol;  in sii3112_reg_read()
113         val = (d->i.bus[0].ifs[0].blk) ? 0x113 : 0;  in sii3112_reg_read()
116         val = (uint32_t)d->regs[0].sien << 16;  in sii3112_reg_read()
119         val = d->regs[1].scontrol;  in sii3112_reg_read()
122         val = (d->i.bus[1].ifs[0].blk) ? 0x113 : 0;  in sii3112_reg_read()
125         val = (uint32_t)d->regs[1].sien << 16;  in sii3112_reg_read()
138     SiI3112PCIState *d = opaque;  in sii3112_reg_write()  local
144         bmdma_cmd_writeb(&d->i.bmdma[0], val);  in sii3112_reg_write()
148         d->regs[0].swdata = val & 0x3f;  in sii3112_reg_write()
152         bmdma_status_writeb(&d->i.bmdma[0], val);  in sii3112_reg_write()
155         bmdma_addr_ioport_ops.write(&d->i.bmdma[0], addr - 4, val, size);  in sii3112_reg_write()
159         bmdma_cmd_writeb(&d->i.bmdma[1], val);  in sii3112_reg_write()
163         d->regs[1].swdata = val & 0x3f;  in sii3112_reg_write()
167         bmdma_status_writeb(&d->i.bmdma[1], val);  in sii3112_reg_write()
170         bmdma_addr_ioport_ops.write(&d->i.bmdma[1], addr - 12, val, size);  in sii3112_reg_write()
173         pci_ide_data_le_ops.write(&d->i.bus[0], addr - 0x80, val, size);  in sii3112_reg_write()
176         pci_ide_cmd_le_ops.write(&d->i.bus[0], 2, val, size);  in sii3112_reg_write()
179         pci_ide_data_le_ops.write(&d->i.bus[1], addr - 0xc0, val, size);  in sii3112_reg_write()
182         pci_ide_cmd_le_ops.write(&d->i.bus[1], 2, val, size);  in sii3112_reg_write()
185         d->regs[0].scontrol = val & 0xfff;  in sii3112_reg_write()
187             ide_bus_reset(&d->i.bus[0]);  in sii3112_reg_write()
191         d->regs[0].sien = (val >> 16) & 0x3eed;  in sii3112_reg_write()
194         d->regs[1].scontrol = val & 0xfff;  in sii3112_reg_write()
196             ide_bus_reset(&d->i.bus[1]);  in sii3112_reg_write()
200         d->regs[1].sien = (val >> 16) & 0x3eed;  in sii3112_reg_write()
251     SiI3112PCIState *d = SII3112_PCI(dev);  in sii3112_pci_realize()  local
261     memory_region_init_io(&d->mmio, OBJECT(d), &sii3112_reg_ops, d,  in sii3112_pci_realize()
263     pci_register_bar(dev, 5, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);  in sii3112_pci_realize()
267     memory_region_init_alias(mr, OBJECT(d), "sii3112.bar0", &d->mmio, 0x80, 8);  in sii3112_pci_realize()
270     memory_region_init_alias(mr, OBJECT(d), "sii3112.bar1", &d->mmio, 0x88, 4);  in sii3112_pci_realize()
273     memory_region_init_alias(mr, OBJECT(d), "sii3112.bar2", &d->mmio, 0xc0, 8);  in sii3112_pci_realize()
276     memory_region_init_alias(mr, OBJECT(d), "sii3112.bar3", &d->mmio, 0xc8, 4);  in sii3112_pci_realize()
279     memory_region_init_alias(mr, OBJECT(d), "sii3112.bar4", &d->mmio, 0, 16);  in sii3112_pci_realize()