Lines Matching +full:d +full:- +full:- +full:- +full:- +full:- +full:0
7 * See the COPYING file in the top-level directory.
20 #include "ide-internal.h"
39 * Internal Register Space - BAR5 (section 6.7 of the data sheet).
45 SiI3112PCIState *d = opaque; in sii3112_reg_read() local
49 case 0x00: in sii3112_reg_read()
50 val = d->i.bmdma[0].cmd; in sii3112_reg_read()
52 case 0x01: in sii3112_reg_read()
53 val = d->regs[0].swdata; in sii3112_reg_read()
55 case 0x02: in sii3112_reg_read()
56 val = d->i.bmdma[0].status; in sii3112_reg_read()
58 case 0x03: in sii3112_reg_read()
59 val = 0; in sii3112_reg_read()
61 case 0x04 ... 0x07: in sii3112_reg_read()
62 val = bmdma_addr_ioport_ops.read(&d->i.bmdma[0], addr - 4, size); in sii3112_reg_read()
64 case 0x08: in sii3112_reg_read()
65 val = d->i.bmdma[1].cmd; in sii3112_reg_read()
67 case 0x09: in sii3112_reg_read()
68 val = d->regs[1].swdata; in sii3112_reg_read()
70 case 0x0a: in sii3112_reg_read()
71 val = d->i.bmdma[1].status; in sii3112_reg_read()
73 case 0x0b: in sii3112_reg_read()
74 val = 0; in sii3112_reg_read()
76 case 0x0c ... 0x0f: in sii3112_reg_read()
77 val = bmdma_addr_ioport_ops.read(&d->i.bmdma[1], addr - 12, size); in sii3112_reg_read()
79 case 0x10: in sii3112_reg_read()
80 val = d->i.bmdma[0].cmd; in sii3112_reg_read()
81 val |= (d->regs[0].confstat & (1UL << 11) ? (1 << 4) : 0); /*SATAINT0*/ in sii3112_reg_read()
82 val |= (d->regs[1].confstat & (1UL << 11) ? (1 << 6) : 0); /*SATAINT1*/ in sii3112_reg_read()
83 val |= (d->i.bmdma[1].status & BM_STATUS_INT ? (1 << 14) : 0); in sii3112_reg_read()
84 val |= (uint32_t)d->i.bmdma[0].status << 16; in sii3112_reg_read()
85 val |= (uint32_t)d->i.bmdma[1].status << 24; in sii3112_reg_read()
87 case 0x18: in sii3112_reg_read()
88 val = d->i.bmdma[1].cmd; in sii3112_reg_read()
89 val |= (d->regs[1].confstat & (1UL << 11) ? (1 << 4) : 0); in sii3112_reg_read()
90 val |= (uint32_t)d->i.bmdma[1].status << 16; in sii3112_reg_read()
92 case 0x80 ... 0x87: in sii3112_reg_read()
93 val = pci_ide_data_le_ops.read(&d->i.bus[0], addr - 0x80, size); in sii3112_reg_read()
95 case 0x8a: in sii3112_reg_read()
96 val = pci_ide_cmd_le_ops.read(&d->i.bus[0], 2, size); in sii3112_reg_read()
98 case 0xa0: in sii3112_reg_read()
99 val = d->regs[0].confstat; in sii3112_reg_read()
101 case 0xc0 ... 0xc7: in sii3112_reg_read()
102 val = pci_ide_data_le_ops.read(&d->i.bus[1], addr - 0xc0, size); in sii3112_reg_read()
104 case 0xca: in sii3112_reg_read()
105 val = pci_ide_cmd_le_ops.read(&d->i.bus[1], 2, size); in sii3112_reg_read()
107 case 0xe0: in sii3112_reg_read()
108 val = d->regs[1].confstat; in sii3112_reg_read()
110 case 0x100: in sii3112_reg_read()
111 val = d->regs[0].scontrol; in sii3112_reg_read()
113 case 0x104: in sii3112_reg_read()
114 val = (d->i.bus[0].ifs[0].blk) ? 0x113 : 0; in sii3112_reg_read()
116 case 0x148: in sii3112_reg_read()
117 val = (uint32_t)d->regs[0].sien << 16; in sii3112_reg_read()
119 case 0x180: in sii3112_reg_read()
120 val = d->regs[1].scontrol; in sii3112_reg_read()
122 case 0x184: in sii3112_reg_read()
123 val = (d->i.bus[1].ifs[0].blk) ? 0x113 : 0; in sii3112_reg_read()
125 case 0x1c8: in sii3112_reg_read()
126 val = (uint32_t)d->regs[1].sien << 16; in sii3112_reg_read()
129 val = 0; in sii3112_reg_read()
139 SiI3112PCIState *d = opaque; in sii3112_reg_write() local
143 case 0x00: in sii3112_reg_write()
144 case 0x10: in sii3112_reg_write()
145 bmdma_cmd_writeb(&d->i.bmdma[0], val); in sii3112_reg_write()
147 case 0x01: in sii3112_reg_write()
148 case 0x11: in sii3112_reg_write()
149 d->regs[0].swdata = val & 0x3f; in sii3112_reg_write()
151 case 0x02: in sii3112_reg_write()
152 case 0x12: in sii3112_reg_write()
153 bmdma_status_writeb(&d->i.bmdma[0], val); in sii3112_reg_write()
155 case 0x04 ... 0x07: in sii3112_reg_write()
156 bmdma_addr_ioport_ops.write(&d->i.bmdma[0], addr - 4, val, size); in sii3112_reg_write()
158 case 0x08: in sii3112_reg_write()
159 case 0x18: in sii3112_reg_write()
160 bmdma_cmd_writeb(&d->i.bmdma[1], val); in sii3112_reg_write()
162 case 0x09: in sii3112_reg_write()
163 case 0x19: in sii3112_reg_write()
164 d->regs[1].swdata = val & 0x3f; in sii3112_reg_write()
166 case 0x0a: in sii3112_reg_write()
167 case 0x1a: in sii3112_reg_write()
168 bmdma_status_writeb(&d->i.bmdma[1], val); in sii3112_reg_write()
170 case 0x0c ... 0x0f: in sii3112_reg_write()
171 bmdma_addr_ioport_ops.write(&d->i.bmdma[1], addr - 12, val, size); in sii3112_reg_write()
173 case 0x80 ... 0x87: in sii3112_reg_write()
174 pci_ide_data_le_ops.write(&d->i.bus[0], addr - 0x80, val, size); in sii3112_reg_write()
176 case 0x8a: in sii3112_reg_write()
177 pci_ide_cmd_le_ops.write(&d->i.bus[0], 2, val, size); in sii3112_reg_write()
179 case 0xc0 ... 0xc7: in sii3112_reg_write()
180 pci_ide_data_le_ops.write(&d->i.bus[1], addr - 0xc0, val, size); in sii3112_reg_write()
182 case 0xca: in sii3112_reg_write()
183 pci_ide_cmd_le_ops.write(&d->i.bus[1], 2, val, size); in sii3112_reg_write()
185 case 0x100: in sii3112_reg_write()
186 d->regs[0].scontrol = val & 0xfff; in sii3112_reg_write()
188 ide_bus_reset(&d->i.bus[0]); in sii3112_reg_write()
191 case 0x148: in sii3112_reg_write()
192 d->regs[0].sien = (val >> 16) & 0x3eed; in sii3112_reg_write()
194 case 0x180: in sii3112_reg_write()
195 d->regs[1].scontrol = val & 0xfff; in sii3112_reg_write()
197 ide_bus_reset(&d->i.bus[1]); in sii3112_reg_write()
200 case 0x1c8: in sii3112_reg_write()
201 d->regs[1].sien = (val >> 16) & 0x3eed; in sii3112_reg_write()
217 int i, set = 0; in sii3112_update_irq()
219 for (i = 0; i < 2; i++) { in sii3112_update_irq()
220 set |= s->regs[i].confstat & (1UL << 11); in sii3112_update_irq()
222 pci_set_irq(PCI_DEVICE(s), (set ? 1 : 0)); in sii3112_update_irq()
231 s->regs[channel].confstat |= (1UL << 11); in sii3112_set_irq()
233 s->regs[channel].confstat &= ~(1UL << 11); in sii3112_set_irq()
244 for (i = 0; i < 2; i++) { in sii3112_reset()
245 s->regs[i].confstat = 0x6515 << 16; in sii3112_reset()
246 ide_bus_reset(&s->i.bus[i]); in sii3112_reset()
252 SiI3112PCIState *d = SII3112_PCI(dev); in sii3112_pci_realize() local
258 pci_config_set_interrupt_pin(dev->config, 1); in sii3112_pci_realize()
259 pci_set_byte(dev->config + PCI_CACHE_LINE_SIZE, 8); in sii3112_pci_realize()
262 memory_region_init_io(&d->mmio, OBJECT(d), &sii3112_reg_ops, d, in sii3112_pci_realize()
263 "sii3112.bar5", 0x200); in sii3112_pci_realize()
264 pci_register_bar(dev, 5, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); in sii3112_pci_realize()
266 /* BAR0-BAR4 are PCI I/O space aliases into BAR5 */ in sii3112_pci_realize()
268 memory_region_init_alias(mr, OBJECT(d), "sii3112.bar0", &d->mmio, 0x80, 8); in sii3112_pci_realize()
269 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, mr); in sii3112_pci_realize()
271 memory_region_init_alias(mr, OBJECT(d), "sii3112.bar1", &d->mmio, 0x88, 4); in sii3112_pci_realize()
274 memory_region_init_alias(mr, OBJECT(d), "sii3112.bar2", &d->mmio, 0xc0, 8); in sii3112_pci_realize()
277 memory_region_init_alias(mr, OBJECT(d), "sii3112.bar3", &d->mmio, 0xc8, 4); in sii3112_pci_realize()
280 memory_region_init_alias(mr, OBJECT(d), "sii3112.bar4", &d->mmio, 0, 16); in sii3112_pci_realize()
284 for (i = 0; i < 2; i++) { in sii3112_pci_realize()
285 ide_bus_init(&s->bus[i], sizeof(s->bus[i]), ds, i, 1); in sii3112_pci_realize()
286 ide_bus_init_output_irq(&s->bus[i], qdev_get_gpio_in(ds, i)); in sii3112_pci_realize()
288 bmdma_init(&s->bus[i], &s->bmdma[i], s); in sii3112_pci_realize()
289 ide_bus_register_restart_cb(&s->bus[i]); in sii3112_pci_realize()
298 pd->vendor_id = 0x1095; in sii3112_pci_class_init()
299 pd->device_id = 0x3112; in sii3112_pci_class_init()
300 pd->class_id = PCI_CLASS_STORAGE_RAID; in sii3112_pci_class_init()
301 pd->revision = 1; in sii3112_pci_class_init()
302 pd->realize = sii3112_pci_realize; in sii3112_pci_class_init()
304 dc->desc = "SiI3112A SATA controller"; in sii3112_pci_class_init()
305 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); in sii3112_pci_class_init()