107 static uint64_t amdvi_readq(AMDVIState *s, hwaddr addr)  in amdvi_readq()  function
149     return amdvi_readq(s, addr) | val;  in amdvi_test_mask()
155     amdvi_writeq_raw(s, addr, amdvi_readq(s, addr) | val);  in amdvi_assign_orq()
161    amdvi_writeq_raw(s, addr, amdvi_readq(s, addr) & val);  in amdvi_assign_andq()
563         trace_amdvi_command_error(amdvi_readq(s, AMDVI_MMIO_CONTROL));  in amdvi_cmdbuf_run()
610         val = amdvi_readq(s, addr);  in amdvi_mmio_read()
619     unsigned long control = amdvi_readq(s, AMDVI_MMIO_CONTROL);  in amdvi_handle_control_write()
651     uint64_t val = amdvi_readq(s, AMDVI_MMIO_DEVICE_TABLE);  in amdvi_handle_devtab_write()
662     s->cmdbuf_head = amdvi_readq(s, AMDVI_MMIO_COMMAND_HEAD)  in amdvi_handle_cmdhead_write()
669     s->cmdbuf = amdvi_readq(s, AMDVI_MMIO_COMMAND_BASE)  in amdvi_handle_cmdbase_write()
671     s->cmdbuf_len = 1UL << (amdvi_readq(s, AMDVI_MMIO_CMDBUF_SIZE_BYTE)  in amdvi_handle_cmdbase_write()
678     s->cmdbuf_tail = amdvi_readq(s, AMDVI_MMIO_COMMAND_TAIL)  in amdvi_handle_cmdtail_write()
685     uint64_t val = amdvi_readq(s, AMDVI_MMIO_EXCL_LIMIT);  in amdvi_handle_excllim_write()
692     uint64_t val = amdvi_readq(s, AMDVI_MMIO_EVENT_BASE);  in amdvi_handle_evtbase_write()
694     s->evtlog_len = 1UL << (amdvi_readq(s, AMDVI_MMIO_EVTLOG_SIZE_BYTE)  in amdvi_handle_evtbase_write()
700     uint64_t val = amdvi_readq(s, AMDVI_MMIO_EVENT_TAIL);  in amdvi_handle_evttail_write()
706     uint64_t val = amdvi_readq(s, AMDVI_MMIO_EVENT_HEAD);  in amdvi_handle_evthead_write()
712     uint64_t val = amdvi_readq(s, AMDVI_MMIO_PPR_BASE);  in amdvi_handle_pprbase_write()
714     s->pprlog_len = 1UL << (amdvi_readq(s, AMDVI_MMIO_PPRLOG_SIZE_BYTE)  in amdvi_handle_pprbase_write()
720     uint64_t val = amdvi_readq(s, AMDVI_MMIO_PPR_HEAD);  in amdvi_handle_pprhead_write()
726     uint64_t val = amdvi_readq(s, AMDVI_MMIO_PPR_TAIL);  in amdvi_handle_pprtail_write()