91 static void amdvi_set_quad(AMDVIState *s, hwaddr addr, uint64_t val,  in amdvi_set_quad()
115 static void amdvi_writeq_raw(AMDVIState *s, hwaddr addr, uint64_t val)  in amdvi_writeq_raw()
121 static void amdvi_writew(AMDVIState *s, hwaddr addr, uint16_t val)  in amdvi_writew()
135 static void amdvi_writel(AMDVIState *s, hwaddr addr, uint32_t val)  in amdvi_writel()
149 static void amdvi_writeq(AMDVIState *s, hwaddr addr, uint64_t val)  in amdvi_writeq()
164 static bool amdvi_test_mask(AMDVIState *s, hwaddr addr, uint64_t val)  in amdvi_test_mask()
170 static void amdvi_assign_orq(AMDVIState *s, hwaddr addr, uint64_t val)  in amdvi_assign_orq()
176 static void amdvi_assign_andq(AMDVIState *s, hwaddr addr, uint64_t val)  in amdvi_assign_andq()
646 static void amdvi_mmio_trace_write(hwaddr addr, unsigned size, uint64_t val)  in amdvi_mmio_trace_write()
657     uint64_t val = -1;  in amdvi_mmio_read()  local
708     uint64_t val = amdvi_readq(s, AMDVI_MMIO_DEVICE_TABLE);  in amdvi_handle_devtab_write()  local
742     uint64_t val = amdvi_readq(s, AMDVI_MMIO_EXCL_LIMIT);  in amdvi_handle_excllim_write()  local
749     uint64_t val = amdvi_readq(s, AMDVI_MMIO_EVENT_BASE);  in amdvi_handle_evtbase_write()  local
767     uint64_t val = amdvi_readq(s, AMDVI_MMIO_EVENT_TAIL);  in amdvi_handle_evttail_write()  local
773     uint64_t val = amdvi_readq(s, AMDVI_MMIO_EVENT_HEAD);  in amdvi_handle_evthead_write()  local
779     uint64_t val = amdvi_readq(s, AMDVI_MMIO_PPR_BASE);  in amdvi_handle_pprbase_write()  local
787     uint64_t val = amdvi_readq(s, AMDVI_MMIO_PPR_HEAD);  in amdvi_handle_pprhead_write()  local
793     uint64_t val = amdvi_readq(s, AMDVI_MMIO_PPR_TAIL);  in amdvi_handle_pprtail_write()  local
802 static void amdvi_mmio_reg_write(AMDVIState *s, unsigned size, uint64_t val,  in amdvi_mmio_reg_write()
814 static void amdvi_mmio_write(void *opaque, hwaddr addr, uint64_t val,  in amdvi_mmio_write()