Lines Matching +full:migration +full:- +full:compat +full:- +full:common
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
26 #include "acpi-build.h"
27 #include "acpi-common.h"
29 #include "qemu/error-report.h"
35 #include "hw/acpi/acpi-defs.h"
39 #include "hw/acpi/bios-linker-loader.h"
51 #include "migration/vmstate.h"
52 #include "hw/mem/memory-device.h"
56 #include "hw/hyperv/vmbus-bridge.h"
64 #include "hw/pci-host/i440fx.h"
65 #include "hw/pci-host/q35.h"
66 #include "hw/i386/x86-iommu.h"
68 #include "hw/acpi/aml-build.h"
73 #include "qom/qom-qobject.h"
76 #include "hw/virtio/virtio-iommu.h"
83 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
84 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
140 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old in init_common_fadt_data()
144 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ? in init_common_fadt_data()
160 ((ms->smp.max_cpus > 8) ? in init_common_fadt_data()
187 * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture in init_common_fadt_data()
188 * Flags, bit offset 1 - 8042. in init_common_fadt_data()
201 pm->cpu_hp_io_base = 0; in acpi_get_pm_info()
202 pm->pcihp_io_base = 0; in acpi_get_pm_info()
203 pm->pcihp_io_len = 0; in acpi_get_pm_info()
204 pm->smi_on_cpuhp = false; in acpi_get_pm_info()
205 pm->smi_on_cpu_unplug = false; in acpi_get_pm_info()
208 init_common_fadt_data(machine, obj, &pm->fadt); in acpi_get_pm_info()
211 pm->fadt.rev = 1; in acpi_get_pm_info()
212 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; in acpi_get_pm_info()
219 pm->fadt.reset_reg = r; in acpi_get_pm_info()
220 pm->fadt.reset_val = 0xf; in acpi_get_pm_info()
221 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; in acpi_get_pm_info()
222 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; in acpi_get_pm_info()
223 pm->smi_on_cpuhp = in acpi_get_pm_info()
225 pm->smi_on_cpu_unplug = in acpi_get_pm_info()
228 pm->pcihp_io_base = in acpi_get_pm_info()
230 pm->pcihp_io_len = in acpi_get_pm_info()
236 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); in acpi_get_pm_info()
238 pm->s3_disabled = false; in acpi_get_pm_info()
243 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); in acpi_get_pm_info()
245 pm->s4_disabled = false; in acpi_get_pm_info()
250 pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); in acpi_get_pm_info()
252 pm->s4_val = false; in acpi_get_pm_info()
256 pm->pcihp_bridge_en = in acpi_get_pm_info()
259 pm->pcihp_root_en = in acpi_get_pm_info()
266 info->has_hpet = hpet_find(); in acpi_get_misc_info()
268 info->tpm_version = tpm_get_version(tpm_find()); in acpi_get_misc_info()
317 * we need to change size in the future (breaking cross version migration). in acpi_align_size()
342 * build_prt - Define interrupt routing rules
348 * The hash function is: (slot + pin) & 3 -> "LNK[D|A|B|C]".
367 /* device 1 is the power-management device, needs SCI */ in build_prt()
465 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq)); in build_vmbus_device_aml()
562 * _DIS can be no-op because the interrupt cannot be disabled. in build_gsi_link_dev()
573 /* _CRS method - get current settings */
603 /* _STA method - get status */
649 * so these are no-ops. We only need this link to override the in build_piix4_pci0_int()
682 head = name[3] - base; in append_q35_prt_entry()
685 head = i * -1; in append_q35_prt_entry()
713 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ in build_q35_routing_table()
719 /* PCIe->PCI bridge. use PIRQ[E-H] */ in build_q35_routing_table()
801 if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) { in build_q35_dram_controller()
809 mcfg->base, in build_q35_dram_controller()
810 mcfg->base + mcfg->size - 1, in build_q35_dram_controller()
812 mcfg->size)); in build_q35_dram_controller()
821 mcfg->base, in build_q35_dram_controller()
822 mcfg->base + mcfg->size - 1, in build_q35_dram_controller()
824 mcfg->size)); in build_q35_dram_controller()
864 uint32_t nr_mem = machine->ram_slots; in build_dsdt()
873 AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id, in build_dsdt()
874 .oem_table_id = x86ms->oem_table_id }; in build_dsdt()
886 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); in build_dsdt()
891 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { in build_dsdt()
892 build_acpi_pci_hotplug(dsdt, AML_SYSTEM_IO, pm->pcihp_io_base); in build_dsdt()
900 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); in build_dsdt()
901 aml_append(dev, build_pci_host_bridge_osc_method(!pm->pcihp_bridge_en)); in build_dsdt()
908 if (pm->smi_on_cpuhp) { in build_dsdt()
917 pm->fadt.smi_cmd, in build_dsdt()
918 pm->fadt.smi_cmd, in build_dsdt()
924 aml_int(pm->fadt.smi_cmd), 2)); in build_dsdt()
935 if (pm->pcihp_bridge_en) { in build_dsdt()
936 build_acpi_pci_hotplug(dsdt, AML_SYSTEM_IO, pm->pcihp_io_base); in build_dsdt()
941 if (misc->has_hpet) { in build_dsdt()
954 if (machine->nvdimms_state->is_enabled) { in build_dsdt()
963 if (pcmc->legacy_cpu_hotplug) { in build_dsdt()
964 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); in build_dsdt()
968 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, in build_dsdt()
969 .fw_unplugs_cpu = pm->smi_on_cpu_unplug, in build_dsdt()
972 pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02", in build_dsdt()
976 if (pcms->memhp_io_base && nr_mem) { in build_dsdt()
979 pcms->memhp_io_base); in build_dsdt()
983 bus = PC_MACHINE(machine)->pcibus; in build_dsdt()
985 QLIST_FOREACH(bus, &bus->child, sibling) { in build_dsdt()
996 root_bus_limit = bus_num - 1; in build_dsdt()
1022 /* Expander bridges do not have ACPI PCI Hot-plug enabled */ in build_dsdt()
1033 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, in build_dsdt()
1041 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; in build_dsdt()
1042 uint64_t base = mr->addr; in build_dsdt()
1046 base + memory_region_size(mr) - 1); in build_dsdt()
1063 mcfg.base, mcfg.base + mcfg.size - 1); in build_dsdt()
1081 for (i = 0; i < crs_range_set.io_ranges->len; i++) { in build_dsdt()
1086 0x0000, entry->base, entry->limit, in build_dsdt()
1087 0x0000, entry->limit - entry->base + 1)); in build_dsdt()
1098 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { in build_dsdt()
1103 0, entry->base, entry->limit, in build_dsdt()
1104 0, entry->limit - entry->base + 1)); in build_dsdt()
1111 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { in build_dsdt()
1117 0, entry->base, entry->limit, in build_dsdt()
1118 0, entry->limit - entry->base + 1)); in build_dsdt()
1140 pm->fadt.gpe0_blk.address, in build_dsdt()
1141 pm->fadt.gpe0_blk.address, in build_dsdt()
1143 pm->fadt.gpe0_blk.bit_width / 8) in build_dsdt()
1151 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { in build_dsdt()
1153 pm->pcihp_io_base, pm->pcihp_io_len); in build_dsdt()
1159 if (!pm->s3_disabled) { in build_dsdt()
1168 if (!pm->s4_disabled) { in build_dsdt()
1170 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ in build_dsdt()
1172 aml_append(pkg, aml_int(pm->s4_val)); in build_dsdt()
1189 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg); in build_dsdt()
1198 PCIBus *pbus = PCI_HOST_BRIDGE(pci_host)->bus; in build_dsdt()
1229 if (pcms->sgx_epc.size != 0) { in build_dsdt()
1230 uint64_t epc_base = pcms->sgx_epc.base; in build_dsdt()
1231 uint64_t epc_size = pcms->sgx_epc.size; in build_dsdt()
1242 epc_base + epc_size - 1, 0, epc_size)); in build_dsdt()
1253 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { in build_dsdt()
1257 PCIBus *b = PCI_HOST_BRIDGE(pci_host)->bus; in build_dsdt()
1280 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); in build_dsdt()
1286 * IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a)
1335 log_addr_offset = table_data->len; in build_tpm_tcpa()
1365 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); in build_srat()
1366 int nb_numa_nodes = machine->numa_state->num_nodes; in build_srat()
1367 NodeInfo *numa_info = machine->numa_state->nodes; in build_srat()
1368 AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = x86ms->oem_id, in build_srat()
1369 .oem_table_id = x86ms->oem_table_id }; in build_srat()
1375 for (i = 0; i < apic_ids->len; i++) { in build_srat()
1376 int node_id = apic_ids->cpus[i].props.node_id; in build_srat()
1377 uint32_t apic_id = apic_ids->cpus[i].arch_id; in build_srat()
1386 /* Flags, Table 5-36 */ in build_srat()
1403 /* Flags, Table 5-39 */ in build_srat()
1411 * from 640k-1M and possibly another one from 3.5G-4G. in build_srat()
1414 numa_mem_start = table_data->len; in build_srat()
1418 mem_len = numa_info[i - 1].node_mem; in build_srat()
1424 mem_len -= next_base - HOLE_640K_START; in build_srat()
1426 build_srat_memory(table_data, mem_base, mem_len, i - 1, in build_srat()
1436 mem_len = next_base - HOLE_640K_END; in build_srat()
1440 if (mem_base <= x86ms->below_4g_mem_size && in build_srat()
1441 next_base > x86ms->below_4g_mem_size) { in build_srat()
1442 mem_len -= next_base - x86ms->below_4g_mem_size; in build_srat()
1444 build_srat_memory(table_data, mem_base, mem_len, i - 1, in build_srat()
1447 mem_base = x86ms->above_4g_mem_start; in build_srat()
1448 mem_len = next_base - x86ms->below_4g_mem_size; in build_srat()
1453 build_srat_memory(table_data, mem_base, mem_len, i - 1, in build_srat()
1458 if (machine->nvdimms_state->is_enabled) { in build_srat()
1470 slots = (table_data->len - numa_mem_start) / 40 /* mem affinity len */; in build_srat()
1485 if (machine->device_memory) { in build_srat()
1486 build_srat_memory(table_data, machine->device_memory->base, in build_srat()
1487 memory_region_size(&machine->device_memory->mr), in build_srat()
1488 nb_numa_nodes - 1, in build_srat()
1522 build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1); in insert_scope()
1524 build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1); in insert_scope()
1534 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; in dmar_host_bridges()
1580 build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1); in build_dmar_q35()
1588 16 + ioapic_scope_size + scope_blob->len, 2); in build_dmar_q35()
1597 /* Scope definition for the root-complex IOAPIC. See VT-d spec in build_dmar_q35()
1611 g_array_append_vals(table_data, scope_blob->data, scope_blob->len); in build_dmar_q35()
1614 if (iommu->dt_supported) { in build_dmar_q35()
1628 * (Version 1.0 - April 6, 2009)
1629 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx
1646 * Which avoids costly VMExits caused by guest re-reading it unnecessarily. in build_waet()
1669 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; in insert_ivhd()
1675 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; in insert_ivhd()
1686 * root ports without a slot (ie. built-ins) and Range entries in insert_ivhd()
1687 * when there is a slot. The same system also only hard-codes in insert_ivhd()
1688 * the alias range for an onboard PCIe-to-PCI bridge, apparently in insert_ivhd()
1719 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); in insert_ivhd()
1740 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus; in ivrs_host_bridges()
1761 /* IVinfo - IO virtualization information common to all in build_amd_iommu()
1781 if (!ivhd_blob->len) { in build_amd_iommu()
1784 * These are 4-byte device entries currently reporting the range of in build_amd_iommu()
1785 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) in build_amd_iommu()
1792 * for type IO-APIC in build_amd_iommu()
1793 * Refer to spec - Table 95: IVHD device entry type codes in build_amd_iommu()
1795 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). in build_amd_iommu()
1806 /* IVHD definition - type 10h */ in build_amd_iommu()
1817 build_append_int_noprefix(table_data, ivhd_blob->len + 24, 2); in build_amd_iommu()
1820 object_property_get_int(OBJECT(s->pci), "addr", in build_amd_iommu()
1823 build_append_int_noprefix(table_data, s->pci->capab_offset, 2); in build_amd_iommu()
1825 build_append_int_noprefix(table_data, s->mr_mmio.addr, 8); in build_amd_iommu()
1835 if (s->xtsup) { in build_amd_iommu()
1841 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); in build_amd_iommu()
1843 /* IVHD definition - type 11h */ in build_amd_iommu()
1852 build_append_int_noprefix(table_data, ivhd_blob->len + 40, 2); in build_amd_iommu()
1855 object_property_get_int(OBJECT(s->pci), "addr", in build_amd_iommu()
1858 build_append_int_noprefix(table_data, s->pci->capab_offset, 2); in build_amd_iommu()
1860 build_append_int_noprefix(table_data, s->mr_mmio.addr, 8); in build_amd_iommu()
1875 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); in build_amd_iommu()
1905 mcfg->base = qnum_get_uint(qobject_to(QNum, o)); in acpi_get_mcfg()
1907 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { in acpi_get_mcfg()
1913 mcfg->size = qnum_get_uint(qobject_to(QNum, o)); in acpi_get_mcfg()
1923 DeviceState *iommu = pcms->iommu; in acpi_build()
1931 GArray *tables_blob = tables->table_data; in acpi_build()
1945 oem_id = x86ms->oem_id; in acpi_build()
1951 oem_table_id = x86ms->oem_table_id; in acpi_build()
1958 bios_linker_loader_alloc(tables->linker, in acpi_build()
1968 facs = tables_blob->len; in acpi_build()
1972 dsdt = tables_blob->len; in acpi_build()
1973 build_dsdt(tables_blob, tables->linker, &pm, &misc, in acpi_build()
1981 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id); in acpi_build()
1984 acpi_build_madt(tables_blob, tables->linker, x86ms, in acpi_build()
1985 x86ms->oem_id, x86ms->oem_table_id); in acpi_build()
1993 build_erst(tables_blob, tables->linker, erst_dev, in acpi_build()
1994 x86ms->oem_id, x86ms->oem_table_id); in acpi_build()
2003 tables->vmgenid, tables->linker, x86ms->oem_id); in acpi_build()
2009 vmclock_build_acpi(VMCLOCK(vmclock_dev), tables_blob, tables->linker, in acpi_build()
2010 x86ms->oem_id); in acpi_build()
2015 build_hpet(tables_blob, tables->linker, x86ms->oem_id, in acpi_build()
2016 x86ms->oem_table_id); in acpi_build()
2022 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog, in acpi_build()
2023 x86ms->oem_id, x86ms->oem_table_id); in acpi_build()
2026 build_tpm2(tables_blob, tables->linker, tables->tcpalog, in acpi_build()
2027 x86ms->oem_id, x86ms->oem_table_id); in acpi_build()
2031 if (machine->numa_state->num_nodes) { in acpi_build()
2033 build_srat(tables_blob, tables->linker, machine); in acpi_build()
2034 if (machine->numa_state->have_numa_distance) { in acpi_build()
2036 build_slit(tables_blob, tables->linker, machine, x86ms->oem_id, in acpi_build()
2037 x86ms->oem_table_id); in acpi_build()
2039 if (machine->numa_state->hmat_enabled) { in acpi_build()
2041 build_hmat(tables_blob, tables->linker, machine->numa_state, in acpi_build()
2042 x86ms->oem_id, x86ms->oem_table_id); in acpi_build()
2047 build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id, in acpi_build()
2048 x86ms->oem_table_id); in acpi_build()
2052 build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id, in acpi_build()
2053 x86ms->oem_table_id); in acpi_build()
2056 build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id, in acpi_build()
2057 x86ms->oem_table_id); in acpi_build()
2062 build_viot(machine, tables_blob, tables->linker, pci_get_bdf(pdev), in acpi_build()
2063 x86ms->oem_id, x86ms->oem_table_id); in acpi_build()
2065 if (machine->nvdimms_state->is_enabled) { in acpi_build()
2066 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, in acpi_build()
2067 machine->nvdimms_state, machine->ram_slots, in acpi_build()
2068 x86ms->oem_id, x86ms->oem_table_id); in acpi_build()
2070 if (pcms->cxl_devices_state.is_enabled) { in acpi_build()
2071 cxl_build_cedt(table_offsets, tables_blob, tables->linker, in acpi_build()
2072 x86ms->oem_id, x86ms->oem_table_id, &pcms->cxl_devices_state); in acpi_build()
2076 build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id); in acpi_build()
2087 rsdt = tables_blob->len; in acpi_build()
2088 build_rsdt(tables_blob, tables->linker, table_offsets, in acpi_build()
2095 .oem_id = x86ms->oem_id, in acpi_build()
2099 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); in acpi_build()
2113 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); in acpi_build()
2125 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ in acpi_ram_update()
2128 memcpy(memory_region_get_ram_ptr(mr), data->data, size); in acpi_ram_update()
2138 if (!build_state || build_state->patched) { in acpi_build_update()
2141 build_state->patched = 1; in acpi_build_update()
2147 acpi_ram_update(build_state->table_mr, tables.table_data); in acpi_build_update()
2149 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); in acpi_build_update()
2151 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); in acpi_build_update()
2158 build_state->patched = 0; in acpi_build_reset()
2183 if (!x86ms->fw_cfg) { in acpi_setup()
2188 if (!pcms->acpi_build_enabled) { in acpi_setup()
2204 build_state->table_mr = acpi_add_rom_blob(acpi_build_update, in acpi_setup()
2207 assert(build_state->table_mr != NULL); in acpi_setup()
2209 build_state->linker_mr = in acpi_setup()
2211 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE); in acpi_setup()
2214 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, in acpi_setup()
2215 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); in acpi_setup()
2224 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config", in acpi_setup()
2231 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg, in acpi_setup()
2235 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, in acpi_setup()